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Thread: Stanford 'high rise' chip design uses nanoscale 'elevators'

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    Stanford 'high rise' chip design uses nanoscale 'elevators'

    May allow chip makers to "put the power of a supercomputer in your hand".
    Read more.

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    Re: Stanford 'high rise' chip design uses nanoscale 'elevators'

    Wow. These boffins can't half do some impressive things, but can it run Crysis?
    Kickstarters Pledged:
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    Re: Stanford 'high rise' chip design uses nanoscale 'elevators'

    Quote Originally Posted by Lord Midas View Post
    Wow. These boffins can't half do some impressive things, but can it run Crysis?
    Probably 3 separate versions of Crysis all running at 4k on max settings while rendering 5 8k videos and making you coffee.

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    Re: Stanford 'high rise' chip design uses nanoscale 'elevators'

    Stacking seems a really good idea for things like flash chips. I don't see how it can work for a desktop CPU though, where you already have a problem getting rid of all the heat.

    Perhaps if the CPUs are all very low power then you could stack a lot of them, but then you can only run your three versions of Crysis at lowest settings.

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    Re: Stanford 'high rise' chip design uses nanoscale 'elevators'

    Quote Originally Posted by Tabbykatze View Post
    Probably 3 separate versions of Crysis all running at 4k on max settings while rendering 5 8k videos and making you coffee.
    But can it do it on a cold rainy night in Stoke?
    Last edited by Jowsey; 15-12-2014 at 09:48 PM.

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    Re: Stanford 'high rise' chip design uses nanoscale 'elevators'

    Quote Originally Posted by DanceswithUnix View Post
    Stacking seems a really good idea for things like flash chips. I don't see how it can work for a desktop CPU though, where you already have a problem getting rid of all the heat.
    This is why you need a team of Stanford scientists, if it was easy everyone would be doing it.

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    Re: Stanford 'high rise' chip design uses nanoscale 'elevators'

    Hmm, reminds me of the t-1000's cpu from terminator 2

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    Re: Stanford 'high rise' chip design uses nanoscale 'elevators'

    Quote Originally Posted by DemonHighwayman View Post
    Hmm, reminds me of the t-1000's cpu from terminator 2
    The chip you see is arnies which is model 101 not t-1000

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    Re: Stanford 'high rise' chip design uses nanoscale 'elevators'

    Quote Originally Posted by ElManCub View Post
    The chip you see is arnies which is model 101 not t-1000
    That's right, haven't seen it for ages and am beginning to forget the details. At least you knew what I meant.

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    Re: Stanford 'high rise' chip design uses nanoscale 'elevators'

    i wonder whqt is the difference between rram and sram memory production. i suppose rram is more expensive as sram is currently manufactured memory.

    as for heat concerns, its quiet ok if they stack the cpu on the memory - memory is not heating that much so it should be acceptable.
    yet there is another question, does rram will survive cpu heat?

    We have 3d memory in production already. doing that for cpu was obvious, knowing how it works for memory. i am just supprised it is not from intell nor ibm. are they slacking off with R&D?

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    Re: Stanford 'high rise' chip design uses nanoscale 'elevators'

    Quote Originally Posted by Slivver View Post
    This is why you need a team of Stanford scientists, if it was easy everyone would be doing it.
    lol, OK let me put it another way.

    Take just 4 Intel CPUs, make them 45W power efficient ones to make it easier. That is a total of 180W, and still not a "supercomputer in your hand". Drop the power consumption to Atom cpu levels and, well, I can't imagine any number of those CPUs that I would call a supercomputer.

    So "Supercomputer in your hand, apart from that big radiator, coolant pump and reservoir it has to be plumbed into" I can accept, but it isn't a useful step forward.

    You hear of research in this sort of stuff that gets you eg a stacked CPU, flash, ram and radio circuit so you can make a really small mobile device. I suppose that doesn't grab the headlines (or clicks) and get you future funding though.

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    Re: Stanford 'high rise' chip design uses nanoscale 'elevators'

    I'm sure Cambridge university had done this over a year ago..

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