JEDEC says DDR5 and NVDIMM-P standards will be ready next year

[HEXUS]

DDR5 memory will provide double the bandwidth and density over DDR4.

Read more.

[CAPTAIN_ALLCAPS]

Well hopefully they release some futureproof timings for once so we don't have to keep messing around with XMP and the like.

Then again I've never understood why they use 33MHz steps for their base clocks either; it creates some needlessly strange FSB : DRAM ratios when AMD and Intel use 100/200MHz base clocks.

[scaryjim]

... Then again I've never understood why they use 33MHz steps for their base clocks either ...

If you'd been an overclocker 10 or more years ago you would - or indeed 6 or more years ago, given that Intel only settled on a 100MHz base clock with Sandy Bridge in January 2011. The earlier Core i chips were 133MHz, and Core 2 FSB could be 200, 266, 333 or 400 MHz.

AMD, OTOH, settled on 200MHz base clock when it did away with FSBs for Athlon 64, almost 15 years ago, and have been playing with unusual memory dividers ever since...!

[CAPTAIN_ALLCAPS]

If you'd been an overclocker 10 or more years ago you would - or indeed 6 or more years ago, given that Intel only settled on a 100MHz base clock with Sandy Bridge in January 2011. The earlier Core i chips were 133MHz, and Core 2 FSB could be 200, 266, 333 or 400 MHz.

AMD, OTOH, settled on 200MHz base clock when it did away with FSBs for Athlon 64, almost 15 years ago, and have been playing with unusual memory dividers ever since...!

2011 is a long time ago in the computing world; the DDR4 specs were finalised some 45 months later in September 2014 and Intel must have made their new platform structure known long before Sandy Bridge hit the shelves.

[jnutt]

Not even on DDR4 yet....

[scaryjim]

... the DDR4 specs were finalised some 45 months later in September 2014 and Intel must have made their new platform structure known long before Sandy Bridge hit the shelves.

Oh, absolutely, not arguing that - just that a lot of tech standards are very slow to change, and it's not that long ago in real terms that mainstream CPUs were using a 133MHz base clock.

AFAIK the JEDEC DDR standards are intended to be a continuous evolution, so I suspect there's an underlying timing spec that uses a 33MHz (or possibly 133MHz) tick that's core to the specification and would be a major revision to alter. After all, the interface between the memory controller and the CPU isn't JEDEC's concern - they just specify how the memory clocks. So there's no good reason they should create specifications just to pander to the whims of x86 computing manufacturers. It's not even as if the majority of computing devices are x86...