care to explain please?
I'm lost
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care to explain please?
I'm lost
A resonant global clock-distribution network operating at 4.6GHz is designed in a 90nm 1.0V CMOS technology. Unique to this approach is the set of on-chip spiral inductors that resonate with the clock capacitance, resulting in 20% recycling of global clock power.
any the wiser ?
No, nor me.
http://www.cyclos-semi.com/faqs/
Time to read the FAQ...
[EDIT] No... even that is sparse on information...
Basically they've built inductors into the clock tree (the network of metal that connects the clock signal to the flip-flops it's clocking) to reduce the power required to run a clock.
Charging and discharging a large network of metal (switching it between '1' and '0') at several GHz uses a lot of power :)
/swooosh
that was something going straight over my head again.
the marketing hype implies that, somehow, these flip flop cycles might carry some kind of ... intertia.. that you can use once you back off the throttle.. like a large mass flywheel on a car helps you get up a hill.
kinda thing....
or am I trilliomillions on nano's away....
Whatever AMD has done the performance increase looks decent:
http://www.tomshardware.com/reviews/...r,3202-13.html
The A10-4600M has a 35W TDP and the A8-3500M has a 35W TDP too. There is one higher 35W TDP A8 model which is clocked 100MHZ higher.
All the fastest mobile Llano CPUs have 45W TDPs.
It seems performance/watt of the CPU has gone up a decent amount.
http://media.bestofmicro.com/A/U/337...er-gamingL.png
http://media.bestofmicro.com/A/T/337...wer-gaming.png
http://media.bestofmicro.com/A/S/337...20-%20WebL.png
http://media.bestofmicro.com/A/R/337...%20-%20Web.png
http://media.bestofmicro.com/A/Q/337...-%20VideoL.png
http://media.bestofmicro.com/A/P/337...0-%20Video.png
CAT that's lush. .... But so is balancing the throttle on an old tvr while not QUITE killing yaself.... But i can explain that .... I can't get my head around how this new tech works
To put it basically,it means AMD clock the chip higher using less power consumed than if they didn't use the technology.
"Fundamental to Piledriver is a significant switch in the type of flip-flops used throughout the design. Flip-flops, or flops as they are commonly called, are simple pieces of logic that store some form of data or state. In a microprocessor they can be found in many places, including the start and end of a pipeline stage. Work is done prior to a flop and committed to at the flop or array of flops. The output of these flops becomes the input to the next array of logic. Normally flops are hard edge elements—data is latched at the rising edge of the clock.
In very high frequency designs however, there can be a considerable amount of variability or jitter in the clock. You either have to spend a lot of time ensuring that your design can account for this jitter, or you can incorporate logic that's more tolerant of jitter. The former requires more effort, while the latter burns more power. Bulldozer opted for the latter.
In order to get Bulldozer to market as quickly as possible, after far too many delays, AMD opted to use soft edge flops quite often in the design. Soft edge flops are the opposite of their harder counterparts; they are designed to allow the clock signal to spill over the clock edge while still functioning. Piledriver on the other hand was the result of a systematic effort to swap in smaller, hard edge flops where there was timing margin in the design. The result is a tangible reduction in power consumption. Across the board there's a 10% reduction in dynamic power consumption compared to Bulldozer, and some workloads are apparently even pushing a 20% reduction in active power. Given Piledriver's role in Trinity, as a mostly mobile-focused product, this power reduction was well worth the effort."
http://www.anandtech.com/show/5831/a...00m-a-new-hope
Cat, that has nothing to do with resonant clock mesh technology afaik, though as mentioned in the anand review, it's a significant (re)development by itself that helps cut power.
Quick explanation on resonant clock mesh here:
http://www.extremetech.com/computing...ity-above-4ghz
Flywheel analogy is not far off the mark.
It doesn't but Steve talks about flip-flops and the Anandtech article makes it clearer what they are.Quote:
Originally Posted by kalniel
It seems to me something like this...
How fast can you fill and empty a bath of water? Pumping charge into a capacitor is much the same as putting water into a container, to do it fast you need big transistors (big pumps) and lots of metal (large pipes) and expend lots of energy in the pumping.
Now, take a part full bath, put it on wheels, and push it back and forth. Push and pull at just the right speed and watch the water slosh back and forth in the bath, and the sloshing water is doing most for the pushing and pulling for you so you need very little effort. If you look at one end of the bath, it empties and fills over and over just like you wanted.
OFC the trick here is tuning the get the resonance at the frequency you want. I shall be interested to see if this interferes with overclocking because you will need to re-tune the mesh to clock faster.
Where there is electronics, there is always a water analogy trying to get out :D
I like that analogy.
On the subject of tuning the mesh - that will be interesting, and must already be done, otherwise dynamic voltage & frequency scaling wouldn't work so well. I'm guessing the voltage is key there.
It will probably use some programmable inductor technology, but I suspect the details of that are the clever bit that force people to buy the patent :D
Danceswithunix rocks the analogy world...
I'm getting closer to this now.... any more help guys?