AMD - Zen chitchat

[CAT-THE-FIFTH]

Hmm, I might have a go at pixel-counting the die size if no-one beats me to it!

Looks like 8 cores per chiplet then, but I wonder if there's any significance to the chiplets being paired up like that?

I would assume that the chiplet pair is what will be seen in consumer CPUs?? The controller chip could be positioned right underneath it in a consumer Ryzen 2 CPU.

just remember the IF stuff is now on the seperate io chip. The latency for two chiplets should be the same for 1.

I hope so! If latency is cut down between the CCX and the memory,that would help with games.

[watercooled]

I've edited my last post with my die size estimate (around 75mm2). One thing though - I've seen a few places mention the '8 cores per CCX' thing but I can't actually find anywhere that was mentioned in the presentation?

[krustylicious]

One interesting thing for the threadripper 3k series is that quad channel should work better than the 2990wx at 32c .. I'm wondering if they will do a 64c tr next year - if so i think it will have less memory starvation then the 2990wx has.

I'm wondering now about the clock speeds for ryzen 3k series as well, given that the IF is now on a separate die and clocked differently .

[DanceswithUnix]

Removing identical IF from each zen core and moved that to separate chip meant that, reduced space per chiplet, also rumoured is the that IF doesn't scale well to 7nm(so stays in 14nm) that should mean higher clocks.

Am I missing something here, I didn't see the show but the slides say that IF *enables* modularity. They have to glue the cpu chiplet to the iox with something, so they either invent another infinity fabric or they use infinity fabric.

[Corky34]

I don't think you are, iirc each Zen core doesn't have any IF as that's what they connect to, maybe krustylicious has confused the Zen cores with the Zeppelin SOC that the cores 'sit' on, are a part of, or whatever.

What i don't understand is why the need for a separate I/O die, there's four Zen cores per CCX and there's two of those per Zepplin die, but the Zeppelin die already has all the I/O it needs to communicate with another Zeppelin die so why did they (i assume) replicate what is already part of a Zeppelin die?

Having thought about it some more could they have done it simply because they didn't want to unbalance the I/O like they did with ThreadRipper? Having a central I/O means you don't need to route your I/O from a die without I/O to one that does but doesn't it also mean you increase latency across the board as now everything has to go via that central I/O? Added to that is the central I/O probably has limited bandwidth to the outside world.

This new design seem more like a sticking plaster until a new socket comes out.

[krustylicious]

I did say that each chiplet no longer has IF, its now all on the iox .. The thing that i did get confused with, was this, i thought each of the IF blocks would get a zen 2 chiplet (so 16c x8) but its for each ccx. Also i said it may actually save space and replication, i think thats false now.

[kalniel]

Northbridge gets separated out again

[Corky34]

Yea it's difficult to know what they mean when they say 'chiplet', are they talking about a single Zen core (doubtful), are they talking about a CCX, or are they talking about an entire Zeppelin die. If it's a CCX then that would mean they've binned the memory controller, PCIe controller, USB, SM Bus, and everything else that goes along with a single Zeppelin die. If a chiplet is an entire Zeppelin die then the I/O die is just replicating what's already on the chiplet.

[kalniel]

from anandtech:



Each chiplet die has 8 cores.

[CAT-THE-FIFTH]

from anandtech:



Each chiplet die has 8 cores.

The picture has already been posted!!

[CAT-THE-FIFTH]

The chiplet design makes a lot of sense especially when you consider that TSMC is the only fab with useful production levels on a next gen node. Each of them looks to be smaller than an Apple A12 SOC,so yields should be decent. Not all the logic will shrink down in size and power as well going from one node to another. The I/O die is huge. Estimates put it at 300~450MM2. The is noise from Anandtech and even some retired engineers elsewhere,that they think that the I/O die also has L4 cache,and that the chiplets are the cores,L1 to L3 caches and an IF link.

So for a consumer CPU,you will probably have a much smaller I/O dies,but only if they use chiplets for consumer SOCs,because the AM4 CPUs subtrate is somewhat smaller,so I wonder how easy it is to package??

Notice how the controller die is made on GF 14NM and not 12NM,so its almost like AMD is finding away to use WSA too!!

Edit!!

Someone made a comparison picture on OcUK.


The I/O die might only be so large due to the number of IF links and purported L4 cache.



Most of the Ryzen CPU is comprised of the cores(and space around the cores for the interconnects it appears). I/O and other parts look to be a bit less than half the chip,so unless a larger L4 cache is central to the design,a similar I/O controller chip for a consumer Ryzen CPU might not be that large if they choose to go that way OFC.

[krustylicious]

In terms of routing 8x8 dies, using a separate chip, makes sense as it removes the traces from the imposter and onto the die. But it also means am4 will and potentially tr will get separate io chips.

That is the only disadvantage and potential different latencies with the chiplets in that config.

upside
faster clock speeds
Chiplets can be used in am4/tr4/sp3 without any changes and no unused features..

I do think maxon now needs to release cinebench r20 .. the scene used just doesn't cut it for TR upward

[krustylicious]

arggh the forums double posted when i wanted to edit it

Given those "zen cores" are 2x in core size (4 to 8) 16c ryzen is a done thing i believe

[CAT-THE-FIFTH]

In terms of routing 8x8 dies, using a separate chip, makes sense as it removes the traces from the imposter and onto the die. But it also means am4 will and potentially tr will get separate io chips.

That is the only disadvantage and potential different latencies with the chiplets in that config.

upside
faster clock speeds
Chiplets can be used in am4/tr4/sp3 without any changes and no unused features..

I do think maxon now needs to release cinebench r20 .. the scene used just doesn't cut it for TR upward

It depends on how AMD does this - if Ryzen 2 stays at 8C,then 8C and I/O on the same chip would make it tiny,but there would be more 7NM tape-out costs.

If they decide to use chiplets,it means one design,and more importantly they could re-use one CPU chiplet for the CPUs and APUs. So the APU would have one CPU chiplet swapped out for a GPU chiplet.

OTH,maybe Ryzen 2 for desktop won't be a chiplet but a monolithic CPU,but that would make it larger and lower yielding than the CPU cores they are using for server,which is higher margin.

It will be interesting to see how latencies are though,but there have been rumours of IF improvements - if the IF:memory speed ratio is closer to 1,it might actually help get over potential additional latency issues? I dunno.

I just hope before AMD launches consumer Ryzen 2 they try to work though any issues. I also do hope they make sure Nvidia has samples to optimise their drivers on,as unless AMD can beat Nvidia in performance when consumer Ryzen 2 launches,all the CPUs will be benchmarked on Nvidia cards.

[watercooled]

I think some are over-simplifying what 'fabric' means in this context. It is not just a single blog you can strip off the chiplets; of course the chiplets also have a fabric interface on-die. These dies are also not Zeppelin - that was the codename for the first generation 8C Zen die. The codename is not valid here, nor is it a die shrink of the Zen die, not even close. For one it has no memory or PCIe controllers besides the core changes.

They need a separate, large die because IO logic takes a lot of die space as it quite obvious from the photos. PCIe, DDR and off-package IF is different to on-package communication.

Edit: latency should be more consistent given the central, shared memory controllers.

Also, memory:IF ratio was already 1:1 - it was IF:Core that people were highlighting. Don't forget DDR is double-pumped.

[Corky34]

It's only over simplified because it doesn't really matter where the SDF plane is located, what matter is how you attach the group of four cores that make up a CCX to it.

As we don't know how these chiplets are design we don't know how different they are from the current design, however currently IF is not part of a core or a CCX as can be seen in the picture Cat posted, the oblong that contains four cores and the L3 cache has a small section at the top and by the looks of things that's the Cache-Coherent Master (CCM) that connects the CCX to the IF.

Strictly speaking IF is only the pink sections (for on-package) and the yellow section (for inter-socket) in this image.



The question i have is how much of what's in that image outside of the green CCX blocks has been dumped?