AMD - Zen chitchat

[Corky34]

It is next to main memory which needs to be coherent with the L3 cache, so coherency is a wash as the logic is pretty much there anyway.

Northbridge cache is I believe what made the Nvidia chipset motherboards so fast when they came out back in the Athlon era. Usually the L3 cache hides memory accesses of the memory controllers, but if they are on another piece of silicon then they should be tuned to hide the latency of the fabric to the IO controller, the controller can have it's own cache tuned to hide the memory latency also acting as a destination for any prefetchers it might have.

That makes sense, the logic already being there. What gave me pause for thought was more the extra complexity of the traces in the substrate, yes an L3 cache shared between chiplets and an L4 cache within the I/O die is a better solution from a performance perspective but it also means more traces within the substrate as each chiplet has to have two connections, one for connecting to all other chiplets and another for connecting to the I/O die.

[scaryjim]

… I hadn't seen it mentioned here yet, but did you see what Anandtech said about the power?! They estimate it's nearly twice as energy efficient compared to a 9900K during Cinebench. That's got to be one of the gains by going with mixed die processes - you can keep each in the preferred power-frequency window without having to compromise quite so much.

I believe the estimate was 75W at performance equity. It's pretty insane, given what Intel do to their TDP definitions (iirc the 9900k actually pulls around 130W peak for the test). Of course part of that on n-thread tests is the comparative efficiency of AMD's SMT implementation, which I do wonder if they've tweaked further. But I'm sure that using different processes for the different structures has all sorts of benefits...

Of course if that 75W is accurate they've got another 30W to play with in the TDP stakes. A quick comparison of the 2600 and 2600X (65W v 95W) suggests that might give them as much as 10% additional performance.

Or, to look at it another way, it suggests that any non-X parts (which I'm assuming will come to market with a 65W TDP) will be almost as fast as Intel's fastest available parts.

Chapeau, AMD...

... they should be tuned to hide the latency of the fabric to the IO controller, the controller can have it's own cache tuned to hide the memory latency also acting as a destination for any prefetchers it might have.

Ooooh, now there's interesting …. I'm sure I've read something while I've been looking at all this that says the Ryzen L3 cache - as a victim cache - can't be pre-fetched into? Adding an L4 cache to the IO die that could be prefetched into could really work for them....


EDIT:

No idea why this has only just occurred to me, but by moving to chiplets + IO die, they've totally removed the NUMA considerations from all their processors (well, assuming they make a separate IO die for TR4). Which means the higher core counts should play a lot better with Windows on desktop too....

EDIT 2:

In relation to which, does anyone else get the feeling that this was the real plan for Zen all along, and the monolithic die and MCMs were really just a stop gap while they got their ducks lined up?

[kalniel]

No idea why this has only just occurred to me, but by moving to chiplets + IO die, they've totally removed the NUMA considerations from all their processors (well, assuming they make a separate IO die for TR4). Which means the higher core counts should play a lot better with Windows on desktop too....

EDIT 2:

In relation to which, does anyone else get the feeling that this was the real plan for Zen all along, and the monolithic die and MCMs were really just a stop gap while they got their ducks lined up?

I'm not sure. I think they'd have preferred to get MCMs working better. This is almost like saying we'll hide off-die latency for some threads by giving all threads the same extra latency by making it always off-die. There is still the core-core communication or shared cache lookup to be considered and that's going to take a hit between chiplets.

[Marcvs]

Chiplets make a lot of sense financially and the latency isnt such an issue in a lot of the HPC tasks (that I work on at least), especially when you consider with 64 cores I am going to be able to process much more stuff in parallel.

[scaryjim]

*shrug* I suppose it's going to be another wait and see moment. If they've done a good job it'll just be a great processor - if they've not then it'll be another generation where AMD are the go to for a particular set of workloads without being goods in all workloads.

What I'm finding really interesting is just how much all of this calls back to 5+ years ago and the talking about 2.5D stacking - only back then everyone seemed to assume we'd be using interposers, and here were are still wiring everything through the substrate.I can only assume that's basically because there's no significant performance advantage to interposers at this scale and they would introduce significant additional cost, but - just like jetpacks and martian colonies - I can't help feeling lied to...

[Corky34]

I think it's more to do with how much they've managed to reduce the size of the traces, going from memory the smallest wires were around 30um 5-10 years ago and now days it's around 3um.

Personally I'm looking forward to when we get to the stage of stacking memory (cache) on-top or under the silicon doing the work using TSV's, although that maybe head in the clouds thinking.

[DanceswithUnix]

Personally I'm looking forward to when we get to the stage of stacking memory (cache) on-top or under the silicon doing the work using TSV's, although that maybe head in the clouds thinking.

My worry with that is that at the high end CPU design has a large element of heat and power management. Stacking something on top of the CPU stops the heat getting out, under stops power getting in. We already have mobile/laptop centric chips at the expense of desktop performance, I fear that would be another example.

[Corky34]

Yes re: the heat getting out but no re: the power getting in, that's what TSV's are for.

I should note it's not something i expect to see happening soon (next decade) but it's something I'd like to live long enough to see, there's a lot of barriers/problems to sort out before that happens though.

Shrinking nodes only get you so far, even Gordon Moore hypothesised that there would come a time where we'd need to start building up and out because eventually making things smaller only gets you so far, i mean he was out by a few decades but he can't get everything right.

[scaryjim]

Yes re: the heat getting out but no re: the power getting in, that's what TSV's are for. ...

Warm silicon is not a superconductor

Any additional layer or transport is going to have an impact on power transmission. That's basic physics. How significant that impact is will vary depending on what the intervening layers are doing, and it may be that you actually end up with the stack being more efficient overall because you're using shorter TSVs and transports, but to claim that stacking won't have any impact is just naive...

[Corky34]

Phew! Good job i didn't claim that stacking won't have any impact then.

[scaryjim]

Phew! Good job i didn't claim that stacking won't have any impact then.

You really need to work on your clear communication then, because I could've sworn that's exactly what you did in the line I quoted...

[Corky34]

Perhaps you'd like to explain then as saying "the power getting in, that's what TSV's are for" doesn't seem to be saying or even implying that it "won't have any impact".

[scaryjim]

Perhaps you'd like to explain then as saying "the power getting in, that's what TSV's are for" doesn't seem to be saying or even implying that it "won't have any impact".

You were explicitly disagreeing with DwU's point that sticking chips below the CPU silicon would interfere with power delivery. You clearly implied that using TSVs would resolve the problem. You failed to acknowledge that there would be any impact.

If you're only partially disagreeing with someone, it's often a good idea to expand on what you think the situation is, rather than just saying "no"...

[Corky34]

No, i was disagreeing with DwU's point that "Stacking something on top of the CPU stops the heat getting out, under stops power getting in".

[scaryjim]

No, i was disagreeing with DwU's point that "Stacking something on top of the CPU stops the heat getting out, under stops power getting in".

If you were being pedantically literal with his statement, you'd point out that silicon isn't a perfect insulator and heat would happily pass through an additional layer of silicon with appropriate cooling. Sure, it wouldn't be as efficient, but an extra layer of silicon on top of a CPU does not "stop heat getting out".

If you're going to read the statement literally, disagree with both points. If you're going to read it as hyperbole (as I did), disagree with neither point. Agreeing with one and disagreeing with the other makes no sense.

[Corky34]

Is it that you just have some axe to grind with me personally? Because i know you've read my reply to DwU so you know i said "Yes re: the heat getting out but no re: the power getting in, that's what TSV's are for.".

To make that clear and hopefully circumvent further ad homenie attacks such as saying I'm being naive, that there's something wrong with the way i communicate, and that I'm pedantically illiterate allow me to explain: Heat is linear, power is not. So when DwU said "Stacking something on top of the CPU stops the heat getting out" saying yes is entirely correct as the heat at source would not be the same as the heat at the external surface, when DwU said "under stops power getting in" it is also entirely correct to say no as power is a binary, you either have it or you don't.

Is that clear enough for you or would you like to attack me personally some more while completely ignoring someone who said that what you said is "purely a figment of your wonky imagination" and that they "don't need you to tell us that".