Including native support for C++ of all things:
http://www.brightsideofnews.com/news...6gb-gddr5.aspx
Also, if this wasn't enough, apparently it will be demonstrated tonight to the world:
- 3.0 billion transistors
- 40nm TSMC
- 384-bit memory interface
- 512 shader cores [renamed into CUDA Cores]
- 32 CUDA cores per Shader Cluster
- 1MB L1 cache memory [divided into 16KB Cache - Shared Memory]
- 768KB L2 unified cache memory
- Up to 6GB GDDR5 memory
- Half Speed IEEE 754 Double Precision
http://www.fudzilla.com/content/view/15741/1/


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