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Ill make it short.
CPU-Z reports my CPU voltage as 1.152 when the proccesser is idle...When i start Orthos the voltage changes to 1.136. Shouldn't it be lowering the voltage for speedstep and INCREASING it for when the proccesser is being used?!?! :crazy::crazy:
And on a side note, I really don't think it could be a PSU issue...I got rid of my old no-name one and put in a corsair 620HX
The load that is placed on the system when running something like orthos causes a drop in voltage.
Do you have speedstep/C1E etc enabled?
I am doubtful that while the application is reporting a precision of 3 dp (down to 1 millivolt) it is actually capable of measuring to that accuracy, so while the voltage is dropping (slightly only about 10mV and less than 1%) and the sysrtem is operating correctly, I don't think it is worth losing sleep over. As Shaithis ays, the additional load is probably causing this slight drop in voltage.Quote:
Originally Posted by DevilMayCry42
yep, speed-step
CPU-Z always reports fluctuations in voltages. I would not rely on them being accurate tbh.
couldn't put it any better, I still don't know why lot's people use this software, if it's known to be unreliable.Quote:
Originally Posted by s_kinton
CPUz is not 100% accurate. Just an indication imo.
The voltage drop when the CPU is loaded is known as Vdroop
Some motherboards have less vdroop than others, I'll have to quote since I can't post links, but the droop is by design and isn't a cause for concern.
Quote:
CC (Vcore) and Vdroop Explained
Load line droop (or Vdroop) is an inherent part of any Intel power delivery design. A current proportional to the average current of all active channels flows from through load line regulation resistor RFB. The resulting voltage drop across RFB is proportional to the output current, effectively creating an output voltage droop with a steady-state value. Equation 2 dictates the value for RFB that should be choosen to satisfy the Intel VRD specification (the source of RLL) based on a) the number of power delivery phases (N) and b) the equivalent series resistance (ESR) of the inductor used, effectively known as DCR.
The first question that may come to mind is why droop voltage at all. Truthfully, in most cases the designer may determine that a more cost-effective solution can be achieved by adding droop. Droop can help to reduce the output-voltage spike that results from fast load/current demand changes. The magnitude of the spike is proportional to the magnitude of the load swing and the ESR/ESL of the output capacitor(s) selected. By positioning the no-load voltage (VNL) level near the upper specification limit (bound by the Vccmin load line), a larger negative spike can be sustained without crossing the lower limit. By adding a well controlled output impedance (RLL), the output voltage under load can be effectively 'level shifted' down so that a larger positive spike can be sustained without crossing the upper specification limit (such as when the system suddenly leaves a heavy load condition). This makes sense as the heavier the CPU loading the smaller the potential negative spike and vice versa for lower CPU loading/positive spikes. The resulting system is one in which the system operation point is bound by Vccmin and Vccmax at all times (although short excursions above Vccmax are allowed by design).