Read more.If Intel can take two Penryn processors and put them onto a single die, it begs the question, why not three? According to a leaked presentation, that is exactly what the world's biggest semiconductor manufacturer has in store.
Read more.If Intel can take two Penryn processors and put them onto a single die, it begs the question, why not three? According to a leaked presentation, that is exactly what the world's biggest semiconductor manufacturer has in store.
I always thought the process would go 1, 2, 4, 8 etc cores.
Does 6 not seem an unnecessary half way house? Considering that very few programs make use of 4 or even 2 cores fully, is it not a waste of time?
Should the aim not be to focus on the 8 core chips, by which time software programming will have caught up to allow them to be used to their full potential?
The only situation that I can really see them being advantageous would be blade servers as an interim until 8 core processors are available?
I think they're hoping nehalem will arrive before the need for 8 cores.
This is a one die solution, so maybe the step from 2 to 8 cores is a bit ambitious.
With 16 MB of shared L3 and no need to go through the FSB to communicate between cores, I think that any advantages that Opteron had over Core CPU's has just been annihilated.
Now..... Core 2 Hextuplo Extreme edition
Or.... Skulltrail with 12 cores
That'll make a nice machine with 8 idle cores at any time![]()
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space is tight, probably all they could fit.
if you look at the current tasty end of the Xeons, they have 6meg cache, not 4, or 8.
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If you read the article, this isn't a desktop chip, its a drop in for the existing 4-socket boxes based around the Caneland platform.
If you can boost compute density by 50% in your year old box then that is a definate win.
With four sockets you still get plenty cache coheriency traffic over the FSB, especially with a 16MB L3 cache to deal with. The Netburst based Tulsa Xeon MP chips had the same size cache (and were fabbed on 65nm). In applications with hefty memory bandwidth or core-to-core communication requirements the Opteron is still the king.
Last edited by Thorburn; 26-02-2008 at 08:20 AM.
So thats more new socket types on the way then...
Waiting for the memory controller to be part of the die, then we'll really see a jump..
I meant when it filters down![]()
If it filters down you mean....
9MB L2 and 16MB L3 cache means thats going to be a SERIOUSLY big chip, thats almost as much cache in total as a Montecito and will use up over a billion transistors in total.
The Gallatin-2M core filtered down to the desktop as the Pentium 4 Extreme Edition because a flagship was needed to fight the Athlon FX 51, but here I can't see any reason why they would.
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