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About LinkBacksRead more.VIA's Nano processor family, previously known as Isaiah, takes the fight to Intel's Atom.
Read more.VIA's Nano processor family, previously known as Isaiah, takes the fight to Intel's Atom.
i'll believe it when i see it
If they do it right this could be huge, couldn't resist
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TAKTAK.co.ukOriginally Posted by razer121
oh hex, you suspisious, untrusting person. I'm sure its faster, why would they lie!
Thing is, if their able to get a package which has good graphics from nvidia then they do stand a chance. Look at offerings like that atom mini-itx board, the chipset HSF is about 12 times the size of the atom's one.
if VIA can get, in quantity, without restriction, their CPU with nVidia's chipset, to use little power, yet have full hardware acceleration for highdef video too. They might find they have a winner, as long as the battery life oodwill be g. Assuming its considerably cheaper than intels offering, and considering its all 65nm, doubt thats going to happen.
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This is a great development for consumers! Intel (and to a lesser extent, AMD) once again shall have some serious competition in the low power, low cost, low performance market. I'm definitely looking forward to seeing their new product line benchmarked.
By making it fully pin-compatible, VIA is almost certainly hoping that board manufacturers switch to using Nano in the place of C7. The more Nano processors ordered, the lower the individual processor cost, and the more tempting a package it becomes.
Looking at the VIA white paper, it is worth noting that they have big plans for the architecture. Currently it can fetch and decode three instructions per cycle, same as AMD's K10 (and one less than the core 2 microarchitecture). They stress, however, that this is their initial offering, hinting at desires to expand this at a later stage. Their L1 caches are larger than Intel's offering, which should mean a performance boost, however they are exclusive of the contents in L2, which could well complicate going multi-core. Execution-wise, every cycle it can execute two integer operations, a load, a data store, an address store, a 'media' (complex FP/SIMD) and a multiply operation. Intel's core 2, on the other hand, can execute a load, a store, two FP/Integer/SMID operations, and an Integer operation. This makes Intel's design potentially more well-rounded, whilst VIA's Isaiah is best suited to a light FP workload but with lots and lots of branches. The lowest latency on FP instructions out of any x86-64 processor also means less wasted time, and hence potentially faster execution of FP-heavy code.
Edit: I should also mention the fact that Isaiah is an out-of-order processor microarchitecture, similar to the current offerings by Intel and AMD. VIA's old design, the C7, was strictly in-order, which means that instructions it received had to be and could only be executed in the exact order they arrived in. Instructions are never completed instantly, there is a latency of a few clock cycles between the instruction going in, and a usable answer coming out. This means that if the next instruction wanted to use the results, it would have to be held back until the results were available for it. Because the design was in-order, there was nothing that could be done with this unused time, it was simply a 'bubble' of nothingness in the system. In an out-of-order design, however, it can look ahead and rearrange the order of instructions so that instead of having bubbles, code is moved forwards (and potentially backwards) to fill in the gap, so there less wasted power. This means that whilst the old C7 design would have been forced to twiddle it's proverbial thumbs during complex calculations, the Isaiah design can get on with something else.
The power management features are perhaps one of the more exciting aspects, also featuring self-overclocking if it needs the extra power and it can afford the extra heat - as it checks the tempterature beforehand!
It should be noted that Nano is a single core, single thread processor, in comparison to Intel Atom's more varied options, and the mainstream offerings by both AMD and Intel. This could well be the failing of the Nano design, but achieving SMT abilities (be it via multiple threads per core, or multiple cores) would push up the TDP
The market certainly is looking interesting indeed. I suspect that over the next few years, VIA will look to increase their decodes-per-clock up to Intel's 4, and they will need to figure out how to implement SMT to stay truly competitive. If they can do this, however, their speciality in low wattage solutions could well work extremely well for them. I would also suspect that VIA, as they also have mainboard chipset experience, will then look to implement an on-processor memory controller, similar to AMD's designs and the forthcoming Intel Nehalem. This would fit VIA's objectives nicely, as it would allow the TDP of the entire system solution to be lowered, but would mean having to change the pin layout significantly, and as such we will probably have to wait for Isaiah to mature before we see this.
Last edited by Rosaline; 29-05-2008 at 12:17 PM.
nice idea. but they'll keep pushing chrome. the perfect accompaniment to any idt winchip die shrink!
There was a more detailed write up about the Via Nano CPU on Ars Technica a few months back:
Isaiah revealed: VIA's new low-power architecture
...which was entirely based off the white paper. As was my post, but I tied in competitor's architecture and the effects the changes would have
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