News - Piledriver to surpass the 4GHz barrier with Resonant Clock Mesh

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Originally Posted by Scribe

Interestingly, Intel does power down cores completely, AMD transistor tech doesn't (or at least didn't) allow them to turn a core off completely so its TurboCORE lowers the clock instead.

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Bulldozer has power gated cores,Llano does not.

An interesting observation I made is that Bulldozer power idle power consumption when overclocked actually does not increase hugely.

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Originally Posted by Scribe

Interestingly, Intel does power down cores completely, AMD transistor tech doesn't (or at least didn't) allow them to turn a core off completely so its TurboCORE lowers the clock instead.

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Didn't know that Intel also did it "properly". Note that reducing the power-demand/clock-speed is not the same as actually cutting the power off to a core - so I'll argue that if this is what AMD are doing then they aren't actually doing it right. Afaik the later model PowerPC chips (pretty sure Power6, not sure about Power5+) actually do reroute power away from unused cores - very clever, and I've no idea how they do this.

Sorry that this is - strictly speaking - off topic, but it seemed relevant at the time. ;)

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Originally Posted by kalniel

Of course he does. You're just used to seeing the big heXus avatar and 'lowe' username :p

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Originally Posted by CAT-THE-FIFTH

Two Hexus accounts??

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Two different Lowes

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Originally Posted by crossy

Didn't know that Intel also did it "properly". Note that reducing the power-demand/clock-speed is not the same as actually cutting the power off to a core - so I'll argue that if this is what AMD are doing then they aren't actually doing it right. Afaik the later model PowerPC chips (pretty sure Power6, not sure about Power5+) actually do reroute power away from unused cores - very clever, and I've no idea how they do this.

Sorry that this is - strictly speaking - off topic, but it seemed relevant at the time. ;)

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Bulldozer has power gating - cores can be powered down.

In fact when overclocked an FX8150 seems to have lower low idle power consumption than an overclocked Core i5 2500K or Core i7 2600K:

http://hardocp.com/article/2011/10/1...mance_review/9

http://www.tweaktown.com/articles/43...w/index10.html

http://www.bit-tech.net/hardware/cpu...8150-review/10

Most reviews did not look at overclocked idle power consumption.

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Originally Posted by crossy

Didn't know that Intel also did it "properly". Note that reducing the power-demand/clock-speed is not the same as actually cutting the power off to a core - so I'll argue that if this is what AMD are doing then they aren't actually doing it right. Afaik the later model PowerPC chips (pretty sure Power6, not sure about Power5+) actually do reroute power away from unused cores - very clever, and I've no idea how they do this.

Sorry that this is - strictly speaking - off topic, but it seemed relevant at the time. ;)

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Both AMD and Intel fully cut the power to inactive cores. This is called power gating.

Actually, power gating is a bit more general than that. Power gating is removing Vdd to a bunch of transistors by putting a gate in between the supply rail and the transistors in question. There's usually a few transistors that form the power gate. It's the same principle as clock gating... except it's for power.

The granularity at which you apply the gating is the interesting part. Gate off too much in a single swoop and you get weird in-rush effects when you try to charge it all back up too quickly. For example, you might want to power gate your FPU when the decoder sees there are no FPU u-ops in the instruction buffer. Question is how quickly can you power the FPU back up when you see an instruction will need it? It's probably not going to be a single cycle.

I've no idea what the mechanism for power gating at the core-level is, nor how extensive it really is. For example, do registers stay powered to preserve state, or is it lost?

I was going to say maybe they're flushed to a higher level cache but even those can be gated IIRC, so maybe they stay powered?

Llano can do power gating, just not individual cores: http://www.anandtech.com/show/4444/a...apu-a8-3500m/4

Edit: It seems power gating-enabled CPUs have specific 'retention registers' so I was half right: http://en.wikipedia.org/wiki/Power_g...tion_registers

Yeah, lack of per-core low power states (i.e. just having per-socket control) was something that people were bemoaning at the HPC conference I was at the other week.

You can put things like registers and caches into a low power state where you preserve data but cannot access it until you bring the supplies back up to nominal. That in itself presents its own power distribution and design verification issues.

Fascinating thread - thanks all. :hexlub: