News - Micron announces DDR4 module prior to release of official spec.

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Still thinks proposals from the Hybrid Memory Cube Consortium hold more promise.

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Quick, so it is. And here was me being concerned about the cost of upgrading from DDR2 to DDR3 system. May as well wait now. Ivy Bridge with these puppies will be well fast.

Ivy bridge has only a DDR3 controller, it won't support these modules.

I was wondering when DDR4 would be introduced. The industry moved from DDR to DDR2 fairly fast then stopped on DDR3 for ages. Must be what 4 year on DDR3 now, think it was realeased with Nehalem.

Progress is all good, but memory speed makes very little difference anyway, due to all the caching in modern CPUs because the latency to access system RAM is so awful. Modern CPU dies (excluding ones with GPUs included) are pretty much a small amount of execution logic floating in a sea of cache.

That hybrid memory cube stuff sounds ace though. I'd imagine a large cube memory placed within the same package as the CPU die would be pretty ace. Wonder if that'd be possible?

geez, i am still using ddr2. now here comes ddr4 ?

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Originally Posted by Fraz

Progress is all good, but memory speed makes very little difference anyway, due to all the caching in modern CPUs because the latency to access system RAM is so awful. Modern CPU dies (excluding ones with GPUs included) are pretty much a small amount of execution logic floating in a sea of cache.

That hybrid memory cube stuff sounds ace though. I'd imagine a large cube memory placed within the same package as the CPU die would be pretty ace. Wonder if that'd be possible?

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It should make quite a difference for more powerful IGPs though, even Llano benefits from using faster memory.

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Originally Posted by watercooled

It should make quite a difference for more powerful IGPs though, even Llano benefits from using faster memory.

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Good point! I hadn't considered that.

I'll be curious to see what kind of timings these DDR4 modules will run at.

Indeed. What information a GPU will need in the near future is pretty predictable in general so outright speed is probably more important than latency in that case.

I think APU's are all heading the same way though. An extra layer of cache on a different die within the module between the L3 on die and the system memory in the hierachy. More smaller dies is more cost effective than fewer larger ones for both space usage on die and yield on the dies.