MediaTek deca-core MT6797 Helio X20 SoC specs surface

[HEXUS]

Leaked slides provide details of "industry's first Tri-Cluster CPU architecture".

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[keithwalton]

Why on earth would they do 2xA72 + 4xA53 + 4xA53, surely the middle cluster should be A57's I bet only one cluster can be active at a time as well

[Hicks12]

makes no sense, 2x A72 for the high load is fine but a set of 4 2ghz A53 and another 4 1.3ghz A53 cores seems like a complete waste of space... you can simply scale down those 2ghz A53 cores and it will produce the same if not better power efficiency not to mention the use of 4 less cores!

Must be a typo in the slide as I cannot see them using 2 sets of 4 A53 cores at such a similar speed when only one group can be active at a time.. madness.

[DanceswithUnix]

makes no sense, 2x A72 for the high load is fine but a set of 4 2ghz A53 and another 4 1.3ghz A53 cores seems like a complete waste of space... you can simply scale down those 2ghz A53 cores and it will produce the same if not better power efficiency not to mention the use of 4 less cores!

Must be a typo in the slide as I cannot see them using 2 sets of 4 A53 cores at such a similar speed when only one group can be active at a time.. madness.

A53 cores are really small, and if you target one to only be able to do low frequency it will be more efficient.

What I don't get is how you migrate 4 threads onto 2 cores in hardware, so I guess it must appear as a 10 core CPU and just moves threads between cores as required via the OS?