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Thread: TSMC CEO talks about firm's 5nm process plans

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    TSMC CEO talks about firm's 5nm process plans

    Says it will be ready for launch in H1 2020.
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    Re: TSMC CEO talks about firm's 5nm process plans

    WOW! a GTX 980 Ti on 5nm Fab will only need Pci-E bus power to run.

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    Re: TSMC CEO talks about firm's 5nm process plans

    Maybe things have changed or what i read was wrong, but doesn't cost per wafer start climbing when going under, something like, 14nm Finfet? If so I'm not sure the extra power savings would be worth the extra costs.

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    Re: TSMC CEO talks about firm's 5nm process plans

    Quote Originally Posted by Corky34 View Post
    Maybe things have changed or what i read was wrong, but doesn't cost per wafer start climbing when going under, something like, 14nm Finfet? If so I'm not sure the extra power savings would be worth the extra costs.
    Cost per wafer have been climbing for years. If the cost per wafer goes up 50% but you can cram on twice the transistors then your cost per transistor is still better so on things like GPUs it is well worth changing to the new process.

    Problem is, cost per transistor isn't really improving now either. I am expecting some stonking GPUs this summer, but I don't expect bargains.

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    Re: TSMC CEO talks about firm's 5nm process plans

    That's what i must have been thinking of, cost per transistor, i thought historically cost had fallen as fab processes shrunk until we reached 20-28nm, Finfet was a temporary solution to that but it just shifted the size when costs started to climb when going under something like 10nm.

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    Re: TSMC CEO talks about firm's 5nm process plans

    Quote Originally Posted by Corky34 View Post
    That's what i must have been thinking of, cost per transistor, i thought historically cost had fallen as fab processes shrunk until we reached 20-28nm, Finfet was a temporary solution to that but it just shifted the size when costs started to climb when going under something like 10nm.
    Finfet is way of getting around leakage currents that otherwise cause power loss on a modern process. It makes costs worse, but is necessary.

    The cost problem seems to be largely down to the difficulty in using 193nm ultraviolet light to draw features only 14nm across. Immersion lithography helped for a while, using the refractive index of water to shorten the wavelength of light, that bought about 40% improvement. But now, they are using quadruple pattern lithography https://en.wikipedia.org/wiki/Multiple_patterning and the smaller the features are the more masks have to be used. I think that is the crux of the problem, it used to be that you needed harder to make masks from process to process but now you need more of them.

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