Nvidia announces Tesla P100 GPU with Pascal architecture

[Corky34]

It's a mezzanine connector, not an NVlink connector. Nvidia have just chosen the number of pins on it. Just Google mezzanine connector and you'll see tons of them.

I'm not questioning if it's a mezzanine connector, it's both a mezzanine connector and a NVlink connector, in other words it's a NVlink mezzanine connector, as mentioned in the first link i posted "The NVLink interconnect, and the Mezzanine connector represent the first custom interfaces (outside of BGA packaging for their silicon) Nvidia designed."

They're referring to IBM POWER CPUs, as they've partnered up. Intel and AMD are direct Nvidia competitors with no incentive to help them gain market share, IBM is not.

I know they're referring to IBM POWER CPUs, i even said so in brackets, and while it maybe unlikely that Intel or AMD will support NVLink that's an unknown, they may, they may not.

Not true at all as myself and others have explained time and time again. The connection starts and terminates on-die - my point about being able to use a couple of random bits of wire was just to express how untrue it is that the connector is the only important part.

For the end-user the connector is the only important part, that's unless anyone other than NVidia has the ability to disable the NVLink circuitry within Pascal silicon.

It really is as simple as I said - they'd just fuse off the NVlink interface on-die and not connect those pins to anything. The PCIe pins, believe it or not, would be the ones going to the edge connector! Not all pins are terminated at PCIe edge connectors. A huge amount of GPU/CPU pins tend to be power and ground anyway.

Yes and I've said as much when i said "You couldn't just take a P100 and solder the GPU package to a PCB with a PCIe, NVidia could if they wanted but you or I couldn't, that's why i also said "At a guess Nvidia will release a P50 later in the year made from the Pascal silicon that didn't make the cut" GPUs where they've disabled the NVLink circuitry.

This is an early design, testing is critically important, hence I am not just saying I think it is possible I am saying that I bet out there somewhere such adapter boards already exist.

That may well be true but without evidence it's impossible to prove one way or the other, it's like me saying i bet there's an armchair in orbit around Mars, the burden of proof would be on me to prove it, not on you to disprove it.

[scaryjim]

That's just your opinion man.

No, it's not. Words have meanings. If you use them incorrectly people will be confused and argue with you. You are using the words connection and connector wrong. It's really easy to tell this, because half the time you agree with the people you are arguing with, then suddenly you disagree with them again.

Or perhaps watercooled, DancesWithUnix, kalniel and I are all deficient in our understanding of the English language, which is the only other explanation that fits the facts as they stand.

[DanceswithUnix]

That may well be true but without evidence it's impossible to prove one way or the other, it's like me saying i bet there's an armchair in orbit around Mars, the burden of proof would be on me to prove it, not on you to disprove it.

Just citing standard engineering practice for prototype bringup. Plugging things into PCs is normal, almost to the point of boring. Chairs around mars, well that isn't is it. Apply Occam's razor as you see fit.

[watercooled]

I'm not questioning if it's a mezzanine connector, it's both a mezzanine connector and a NVlink connector, in other words it's a NVlink mezzanine connector, as mentioned in the first link i posted "The NVLink interconnect, and the Mezzanine connector represent the first custom interfaces (outside of BGA packaging for their silicon) Nvidia designed.

"For the end-user the connector is the only important part, that's unless anyone other than NVidia has the ability to disable the NVLink circuitry within Pascal silicon.

Where are the QPI or Hypertransport 'connectors' on an Intel or AMD board, respectively? Simply put, there aren't any, the only connection points being in the CPU sockets. NVlink is, as others have said, an interconnect fabric like the aforementioned Intel and AMD ones.

Yes and I've said as much when i said "You couldn't just take a P100 and solder the GPU package to a PCB with a PCIe, NVidia could if they wanted but you or I couldn't,

I'm not sure if you're just being deliberately obtuse here, but you or I probably could do just that with the correct equipment. You'd only really need to get some PCB adapters made and reflow solder the GPU to it. As DancesWithUnix has said, such adapters are ubiquitous in testing labs - they don't install GPUs into a PC and get someone to play games on them in order to test them.

In addition, look at the M.2 > PCIe slot adapters you can get for PCIe SSDs. It's just a dumb PCB with some wire links linking the two connectors. M.2 is just the form factor - the communication protocol is still PCIe through and through.

[Corky34]

No, it's not. Words have meanings. If you use them incorrectly people will be confused and argue with you. You are using the words connection and connector wrong. It's really easy to tell this, because half the time you agree with the people you are arguing with, then suddenly you disagree with them again.

I see you still can't agree to disagree then, you're of course correct when you say words have meanings and I've post links to the meaning of what an electrical connector and what an electrical connection is but for some reason you seem to be saying that their one of the same thing, or at least that's what you appear to have done here...

It doesn't use a conventional PCIe edge/slot connection that conforms with one of the published PCIe standards for connectors. It *does* have an electrical connector for PCIe. It's a non-standard, proprietary connection, but it has one.

Where are the QPI or Hypertransport 'connectors' on an Intel or AMD board, respectively? Simply put, there aren't any, the only connection points being in the CPU sockets. NVlink is, as others have said, an interconnect fabric like the aforementioned Intel and AMD ones.

HyperTransport already has connectors, so does QPI, they may not be on consumer boards, just like NVLink won't be, but there are connectors for both of those in some HPC's.

I'm not sure if you're just being deliberately obtuse here, but you or I probably could do just that with the correct equipment. You'd only really need to get some PCB adapters made and reflow solder the GPU to it. As DancesWithUnix has said, such adapters are ubiquitous in testing labs - they don't install GPUs into a PC and get someone to play games on them in order to test them.

In addition, look at the M.2 > PCIe slot adapters you can get for PCIe SSDs. It's just a dumb PCB with some wire links linking the two connectors. M.2 is just the form factor - the communication protocol is still PCIe through and through.

No I'm not being deliberately obtuse, I've already said ages ago that..."it will eventually come with a PCIe connection (that it's capable of using PCIe) but the first cards are only going to come with NVLink, you or I could probably do anything we like but that's nothing but that's an argument from ignorance, it can't be proven either true or false that you or i could do that without NVidia altering the GPU, even if we had the equipment

[CAT-THE-FIFTH]

BTW,it appears that NO GP100 based gaming parts will be released.

Possible GP106 spotted:

https://translate.googleusercontent....N6sBc01sLJxjpw
https://translate.google.co.uk/trans...-speicher.html

Around 200MM2 with a 128 bit memory controller.

Just made two weeks ago it seems.

[jigger]

BTW,it appears that NO GP100 based gaming parts will be released.

Possible GP106 spotted:

https://translate.googleusercontent....N6sBc01sLJxjpw
https://translate.google.co.uk/trans...-speicher.html

Around 200MM2 with a 128 bit memory controller.

Just made two weeks ago it seems.

Nice find CAT. Although when that guys hold up a chunk of technology you know it's something fishy.

[watercooled]

HyperTransport already has connectors, so does QPI, they may not be on consumer boards, just like NVLink won't be, but there are connectors for both of those in some HPC's.

Ughhhhhhhh...

Have you just dug in so far you refuse to budge or are you just outright trolling now? HT, QPI are most certainly not defined by those connectors. Do you know of the existence of multi-CPU AMD/Intel boards? Guess how the processors communicate with each other? You guessed it, QPI/HT! None of those connectors in sight!

Once again you link to something which contradicts what you're asserting - they're just backplane connectors to extend the reach of the interconnect. It's simply not a matter of opinion, it's just how it is. The Molex backplane one, along with QPI, also equally supports PCIe. How does that fit into your logic?

No I'm not being deliberately obtuse, I've already said ages ago that..."it will eventually come with a PCIe connection (that it's capable of using PCIe) but the first cards are only going to come with NVLink,

That's already being conclusively disproved. The first cards come with and use PCIe - otherwise how do you explain their communication with the PCIe interface on the Intel CPUs? There isn't any sort of NVlink-PCIe bridge chip in the diagrams.

According to Nvidia themselves, it has a PCIe interface, and that's an end to it:

From https://devblogs.nvidia.com/parallel...inside-pascal/

The figure below shows an 8-GPU Hybrid Cube Mesh that includes two fully NVLink-connected quads of GPUs, with NVLink connections between the quads, and GPUs within each quad connected to their respective CPUs directly through PCIe.

I really don't know how much clearer it can be made.

[Corky34]

Ughhhhhhhh...

Have you just dug in so far you refuse to budge or are you just outright trolling now? HT, QPI are most certainly not defined by those connectors. Do you know of the existence of multi-CPU AMD/Intel boards? Guess how the processors communicate with each other? You guessed it, QPI/HT! None of those connectors in sight!


Once again you link to something which contradicts what you're asserting - they're just backplane connectors to extend the reach of the interconnect. It's simply not a matter of opinion, it's just how it is. The Molex backplane one, along with QPI, also equally supports PCIe. How does that fit into your logic?

You asked where the QPI or Hypertransport 'connectors' on an Intel or AMD board are and i gave you information on those respective connections, if you really want i can dig up some links to actual MoBo's that have those connectors directly attached to the PCB but i get the feeling you won't accept that as proof that any of those connection points being outside the CPU sockets.

That's already being conclusively disproved. The first cards come with and use PCIe - otherwise how do you explain their communication with the PCIe interface on the Intel CPUs? There isn't any sort of NVlink-PCIe bridge chip in the diagrams.

According to Nvidia themselves, it has a PCIe interface, and that's an end to it:

From https://devblogs.nvidia.com/parallel...inside-pascal/


I really don't know how much clearer it can be made.

And i don't know how much clearer i can be when i first said "it will eventually come with a PCIe connection (that it's capable of using PCIe) but the first cards are only going to come with NVLink" If that's not correct free to show me a picture of the PC100 where i can make the electrical connection via a PCIe connector.

[watercooled]

You asked where the QPI or Hypertransport 'connectors' on an Intel or AMD board are and i gave you information on those respective connections, if you really want i can dig up some links to actual MoBo's that have those connectors directly attached to the PCB but i get the feeling you won't accept that as proof that any of those connection points being outside the CPU sockets.

You're being silly, anyone with understanding of the subject will tell you the same thing. You've found some connectors which happen to carry the interconnects as an OPTIONAL part, and one seldom used in things like workstations and smaller servers. How do you explain the FACT that CPUs communicate over these links without any such links being present? And the FACT that many devices communicate over protocols like PCIe and USB without a connector in sight?

And i don't know how much clearer i can be when i first said "it will eventually come with a PCIe connection (that it's capable of using PCIe) but the first cards are only going to come with NVLink" If that's not correct free to show me a picture of the PC100 where i can make the electrical connection via a PCIe connector.

The first cards come with PCIe connectivity, what you're saying makes no sense whatsoever. The diagrams very clearly show the GPUs have PCIe connectivity - there's isn't a shred of doubt about that. If you've dug your heels in and don't want to admit it then fair enough, but please do go and read up on PCIe spec if you want to understand what it really is.

Just another example; even the iPhone 6s uses PCIe to communicate with its storage device, not a single PCIe edge connector in sight in that phone funnily enough! http://www.anandtech.com/show/9662/i...minary-results

One notable difference is that this storage solution uses PCI-E rather than SDIO

Or have they squeezed a PCIe slot into the iPhone somehow?

Anyway, I'm done here, we've all simply tried to explain a basic concept but you're just plain refusing to accept the facts presented to you, that's your choice.

[Corky34]

You're being silly, anyone with understanding of the subject will tell you the same thing. You've found some connectors which happen to carry the interconnects as an OPTIONAL part, and one seldom used in things like workstations and smaller servers. How do you explain the FACT that CPUs communicate over these links without any such links being present? And the FACT that many devices communicate over protocols like PCIe and USB without a connector in sight?

You asked where the QPI or Hypertransport 'connectors' are on an Intel or AMD board and i provided examples of such connections, here's another, i don't understand why that's being silly or why you're now placing caveats on what examples are acceptable.

That they're not something that's used in things like workstations and smaller servers seems irrelevant (IMO) as i wouldn't exactly call running eight P100 GPUs in a cluster something that's meant for workstations and smaller servers either.

I never said that many devices don't communicate over protocols like PCIe and USB without a connector in sight, i said from an end-users perspective the protocol being used is irrelevant, that the only time it becomes relevant is when the end-user needs to connect something to the system, and when they do it's still mostly irrelevant as the physical connectors are meant to prevent the end-user connecting two incompatible systems together.

The first cards come with PCIe connectivity, what you're saying makes no sense whatsoever. The diagrams very clearly show the GPUs have PCIe connectivity - there's isn't a shred of doubt about that. If you've dug your heels in and don't want to admit it then fair enough, but please do go and read up on PCIe spec if you want to understand what it really is.

Yes i know they do, and I've repeatedly said they do, I've also been saying they don't come with a PCIe connector, is that not what i said when i said the following...

I get the feeling though that the diagram you/they showed is like some of their other claims, that it will eventually come with a PCIe connection (that it's capable of using PCIe) but the first cards are only going to come with NVLink, i get the feeling that they're fabricating (and initially selling) large silicon and binning ones that don't meet make the grade for a lesser (lower power draw) HPC card that will use PCIe.

Does that not make it clear that the P100 doesn't come with a physical PCIe connector? That the GPU is perfectly capable of using PCIe? That the first cards are only coming with NVLink connectors?

From my perspective it seems that one persons misconception and misinterpretation of what i said has been blown out of all proportions with others deciding to jump on the bandwagon, I've never said the GPU isn't using the PCIe protocol, in fact i believe I've made it perfectly clear that it does, all I've been saying is that the P100 card doesn't have a PCIe connection, that the end-user couldn't plug the card into a PCIe connector, that it lacks the ability to be connected via a standard PCIe interconnect.

[Xlucine]

BTW,it appears that NO GP100 based gaming parts will be released.

Possible GP106 spotted:

https://translate.googleusercontent....N6sBc01sLJxjpw
https://translate.google.co.uk/trans...-speicher.html

Around 200MM2 with a 128 bit memory controller.

Just made two weeks ago it seems.

Ooh, nice find! 128 bit is a bit narrow for a 4TFLOP card. That's half the width with a bit more than a third of the bandwidth of a 970 - nvidia must have dropped the clocks of the memory for power/thermal reasons, since cars must not need as much bandwidth, but it could be odd it the graphics card shares the configuration. I'll wager they've got a 256 bit bus on the die, with half of it fused off for yields

[kalniel]

Ooh, nice find! 128 bit is a bit narrow for a 4TFLOP card. That's half the width with a bit more than a third of the bandwidth of a 970 - nvidia must have dropped the clocks of the memory for power/thermal reasons, since cars must not need as much bandwidth, but it could be odd it the graphics card shares the configuration. I'll wager they've got a 256 bit bus on the die, with half of it fused off for yields

Maybe, but I expect it'll be more like the 960 with the 128bit controller. 970 is 4.2 TFLOPS so if they've upped shader count and speeds a 16FF 1060 could possibly hit 4. Assuming they're talking about per chip, not per dual chip board.

[scaryjim]

... I've never said the GPU isn't using the PCIe protocol, in fact i believe I've made it perfectly clear that it does, all I've been saying is that the P100 card doesn't have a PCIe connection ....

And that's why you're wrong. It must have a connection otherwise it wouldn't have a link to communicate over. Remember this:

... a connection is something that has to be joined, linked, or fastened together ....

The PCIe endpoint in the P100 has to be linked to the PCIe endpoints in the Intel Xeons. That requires a connection. Without a PCIe connection, the P100 could not communicate with the Intel Xeon's because it wouldn't be connected to them.

In the case of the P100, the PCIe connection is carried via a Mezzanine connector. I've said that before. You've said that before. I'm pretty sure we all agree that that's the case.

In which case, your original statement, which you've repeated several times, is wrong, because you said that the P100 doesn't have a PCie connection. By any reasonable definition of that word, it does.

[Corky34]

And that's why you're wrong. It must have a connection otherwise it wouldn't have a link to communicate over. Remember this:

OMG is it impossible for you to agree to disagree?

If as you say "It must have a connection" show me where on the P100 board the end-user would make that connection, show me where the end-user would join, link, or fasten together the P100 card to a PCIe connection.

And before you attempt your usual straw man argument as you've been doing repeatedly throughout this thread you may want to re-read what i originally posted, not what you have repeatedly been quoting out of context.

[DanceswithUnix]

Pascal is going to be released, delays and all, before this argument finishes