7th Generation AMD A-Series desktop PC systems start to ship

[scaryjim]

... Its a shame if AMD does not release them since Kaby Lake will up IGP performance even more for Intel and Kaveri lacks H265 support,etc. ....

Well, I guess it depends on whether they think they'll actually sell in retail vs OEM. The last thing AMD will want in the run up to releasing Zen CPUs and APUs is to have a ton of Bristol Ridge parts in the channel and needing inventory write-down (which is an issue they've had with a couple of APU families recently).

I suppose it would depend on the performance and chip placement. This chip is 28nm and the Zen APU will be 14nm and both are very different designs from what I can tell. An 8 core 16 thread Zen APU might be 95watts

There won't be an 8 core/16 thread APU. The Zen APUs will max out at 4 core/8 thread, with CPUs (no IGP) going up to 8 core/16 thread. It's already been announced that the top TDPs - at least for the initial AM4 offerings - will be 95W - that goes for both APUs and CPUs.

IIRC GDDR3 was ditched with the 5000 series

Yes, fair point - I got lazy when typing about it. Cost saving exercise, I believe...

That's an interesting feature split between CPU/SoC and chipset. Intel's diagrams always show that everything except the PCI-E 16x link goes via chipset and DMI?

Is that a real difference or stuff concealed for marketing?

AFAIK Intel don't currently have any genuine SoCs in the desktop market, and I don't believe they have any SoCs for mobile that use a separate chipset. From what I've read, all AM4 processors are full SoCs - they have a basic southbridge on chip: however I didn't realise that AMD was also enabling them to connect to an external chipset to expand the features on offer. I like the concept - it gives mobo manufacturers ways to differentiate their product lines despite that processors all being full SoCs, from minmalist SFF boards that don't provide any extra chipset features to full enthusiast boards. Very smart move from AMD, IMNSHO...

[ET3D]

Well, I guess it depends on whether they think they'll actually sell in retail vs OEM. The last thing AMD will want in the run up to releasing Zen CPUs and APUs is to have a ton of Bristol Ridge parts in the channel and needing inventory write-down (which is an issue they've had with a couple of APU families recently).

I think they'd actually want a ton of Bristol Ridge parts on the market when releasing Zen, because these will be the low end AM4 chips, with Zen priced at a premium. Zen APU's will appear considerably later.

[ET3D]

By the way, I wonder if we'll see any review of these OEM Bristol Ridge systems or have to wait for the DIY versions. (And even then, I do hope AMD gets MB's and CPU's to reviewers on time.)


Oh, and forgot to thank Hexus (and Mark Tyson) for posting the largest number of slides I've yet see about this.

[scaryjim]

I think they'd actually want a ton of Bristol Ridge parts on the market when releasing Zen, because these will be the low end AM4 chips, with Zen priced at a premium. Zen APU's will appear considerably later.

Hmm, possibly - I guess it depends on what their actual plans are for future APU and CPU releases. e.g. will they bother releasing 4 core versions of the CPUs? I guess the CPUs might get more on-chip PCIe lanes etc. to differentiate from the APU range...?

[DanceswithUnix]

Hmm, possibly - I guess it depends on what their actual plans are for future APU and CPU releases. e.g. will they bother releasing 4 core versions of the CPUs? I guess the CPUs might get more on-chip PCIe lanes etc. to differentiate from the APU range...?

Probably more L3 cache as well, given how the FM2 socket APUs they thought the silicon was better spent on shaders than cache that might not have changed.

[jigger]

There won't be an 8 core/16 thread APU. The Zen APUs will max out at 4 core/8 thread, with CPUs (no IGP) going up to 8 core/16 thread. It's already been announced that the top TDPs - at least for the initial AM4 offerings - will be 95W - that goes for both APUs and CPUs.

I'm sure we will see Zen 8 core APU's at some time, but I was just pointing that I doubt very much doubt a quad core 14nm Zen chip will be 95watts when a 28nm Bristol ridge is 65watts.

[DanceswithUnix]

I'm sure we will see Zen 8 core APU's at some time, but I was just pointing that I doubt very much doubt a quad core 14nm Zen chip will be 95watts when a 28nm Bristol ridge is 65watts.

Perhaps at 7nm, but even then 6 core seems more likely.

[DanceswithUnix]

It looks to me like they have given chipset names (eg A300) to the configuration of not using a chipset and going entirely SoC

Semiaccurate seem to think the chipset is connected by a 4x PCIe3 interface, so freeing up those lanes to directly connect to storage or similar could make sense in some small designs.

[scaryjim]

It looks to me like they have given chipset names (eg A300) to the configuration of not using a chipset and going entirely SoC

That's certainly how I've been reading it, although it begs the question of how you decide whether its an A300, B300 or X300
But for small form factors it makes perfect sense.

My reading of it was also that the storage lanes could be unganged and used for general purpose, so you can have 2 SATA and then have either x2 NVME or use those lanes for peripherals (I note that neither the SoC nor the chipset have ethernet listed...). Also worth noting that the SoC doesn't include USB 3.1 Gen 2 or USB 2.0, so you'll be quite limited for spare ports in a bare SoC implementation. I think you'd need to be able to use those 4 lanes that aren't going to the chipset to add extra peripherals. I suppose that might make it a desirable setup for industrial and specialist applications...

EDIT:

Did some digging around and came up with this image (benchlife.info via wccf):


It's from an old article but seems to match very well with the details released yesterday, and essentially confirms the presence of a Gen 3 x4 PCIe complex that is used to connect to the Promontory chipset where applicable, as well as the 2 additional general purpose PCIe Gen 3 lanes that are part of the storage complex. So I guess that's up to 14 PCIe gen 3 lanes if you don't use a chipset...?

[DanceswithUnix]

So I guess that's up to 14 PCIe gen 3 lanes if you don't use a chipset...?

According to this you get 16 if you sacrifice the 2 SATA ports on the APU, and another 8 if you have Zen:



From http://www.kitguru.net/components/cp...y-pch-usb-3-1/

Edit: Odd, embedded image isn't showing up here. Variant on the picture above though if you can't see it based on the "Summit Ridge" Zen apu.

[jigger]

So if you fully use everything the chipset can offer, you're down to 8 PCIE lanes for the expansion slots with Bristol Ridge and 16 lanes with Zen per module? Drop two SATA connections and then you have 16 and 24?

Is the APU using PCIE for the CPU to talk to the GPU?

[CAT-THE-FIFTH]

Well, I guess it depends on whether they think they'll actually sell in retail vs OEM. The last thing AMD will want in the run up to releasing Zen CPUs and APUs is to have a ton of Bristol Ridge parts in the channel and needing inventory write-down (which is an issue they've had with a couple of APU families recently).

It depends on when the APU is released though. Once Zen CPUs are released,FM2+ is going to look pretty pointless as a platform as it will be EOL,so that leaves the sub £150 market kind of gone for AMD. They do need to release something in that price-range??

[scaryjim]

So if you fully use everything the chipset can offer, you're down to 8 PCIE lanes for the expansion slots with Bristol Ridge and 16 lanes with Zen per module? Drop two SATA connections and then you have 16 and 24?

Not quite. You're limited to a single x8 or single x16 (although if that *can't* be split x8/x8 for multi-GPU I'd be amazed) Gen 3 for dGPU. If you're using a chipset, you get 4 or 6 PCIe gen 2 lanes for peripherals and slots; if not you might be able to use the 4 Gen 3 lanes that usually make up the chipset link (that's not exactly clear). You can always pull off an additional 2 PCIe gen 3 lanes from the storage cluster, but doing so loses you the option of NVMe. So with Bristol Ridge and a chipset (or at least, with the announced chipsets) you have a maximum of 10 PCIe gen 3 lanes (8 of which are a dedicated cluster for dGPU) + 6 PCIe gen 2 lanes - so you could, for instance, have a PCIe3 x8, 2 PCIe 3 x1, a PCIe 2 x4, and 2 PCIe 2 x1 - giving a total of 6 slots (but not much in the way of additional peripheral chips ).

Skylake actually offers less PCIe from the CPU than Summit Ridge - it ONLY does 16 lanes (although it's flexible about how they can be split down). OTOH, the Z170 claims to offer up to 20 PCIe 3 lanes (they get shared out amongst the various peripherals the chipset supports): but since the chipset connects using the same PCIe 3 x4 link that AMD uses, you'd struggle to feed all 20 of those lanes simultaneously.

Is the APU using PCIE for the CPU to talk to the GPU?

Assuming you mean the IGP, not as far as I know. They shared a memory controller and have other direct linkage - they don't need an external bus.

[jigger]

Not quite. You're limited to a single x8 or single x16 (although if that *can't* be split x8/x8 for multi-GPU I'd be amazed) Gen 3 for dGPU. If you're using a chipset, you get 4 or 6 PCIe gen 2 lanes for peripherals and slots; if not you might be able to use the 4 Gen 3 lanes that usually make up the chipset link (that's not exactly clear). You can always pull off an additional 2 PCIe gen 3 lanes from the storage cluster, but doing so loses you the option of NVMe. So with Bristol Ridge and a chipset (or at least, with the announced chipsets) you have a maximum of 10 PCIe gen 3 lanes (8 of which are a dedicated cluster for dGPU) + 6 PCIe gen 2 lanes - so you could, for instance, have a PCIe3 x8, 2 PCIe 3 x1, a PCIe 2 x4, and 2 PCIe 2 x1 - giving a total of 6 slots (but not much in the way of additional peripheral chips ).

Skylake actually offers less PCIe from the CPU than Summit Ridge - it ONLY does 16 lanes (although it's flexible about how they can be split down). OTOH, the Z170 claims to offer up to 20 PCIe 3 lanes (they get shared out amongst the various peripherals the chipset supports): but since the chipset connects using the same PCIe 3 x4 link that AMD uses, you'd struggle to feed all 20 of those lanes simultaneously.



Assuming you mean the IGP, not as far as I know. They shared a memory controller and have other direct linkage - they don't need an external bus.

Cheers. Kinda makes more sense to me.

I have a feeling that diagram might be off though and a might might have changed now Bristol Ridge is using AM4.

[DanceswithUnix]

Cheers. Kinda makes more sense to me.

I have a feeling that diagram might be off though and a might might have changed now Bristol Ridge is using AM4.

The Bristol Ridge silicon is basically the same silicon as Carrizo, so it should be fairly well understood by now, apart from we have only seen Carrizo in a few x4 845 reviews so we don't have anything like the information we should have by now.

[Sunderas]

Interesting but I think I'll wait for the Zen architecture. Anyone knows when they are to come out?