AMD Zen CPU architect Jim Keller becomes an SVP at Intel

[CAT-THE-FIFTH]

As I mentioned elsewhere I suspect he is being hired more for the Intel AI and deep learning projects,as they are plonking a decent amount of money into that,and that is what Jim Keller was working on at Tesla.

Even when it came to AMD,it appears he was mostly working on the K12 ARM core,and Suzanne Plummer and Mike Clark were the main people behind Zen.

til then enjoy those incremental increases and high TDPs trying to keep competitive with the multicore zen disturbers, while doing anything to keep a lead in single thread. Not that Ryzen is perfect, but can you imagine if its single thread had been higher? Ooof.

Its not even the single threaded performance(look at non-gaming scenarios),its more the case,that Ryzen MK1 also had high cache and memory access latency,which did not help in games and the fact that plenty of games are just better optimised for ring bus based CPUs,as you saw the issues with SKL-X in a number of games. The IPC increase in games with the Ryzen 2 CPUs is actually more pronounced than for non-gaming applications and the cache improvements are the biggest ones it appears for Ryzen 2 when compared with Ryzen MK1. It even showed up as huge improvements in DAW benchmarks too.

[Corky34]

As I mentioned elsewhere I suspect he is being hired more for the Intel AI and deep learning projects,as they are plonking a decent amount of money into that,and that is what Jim Keller was working on at Tesla.

Even when it came to AMD,it appears he was mostly working on the K12 ARM core,and Suzanne Plummer and Mike Clark were the main people behind Zen.

He was in charge of the team working on Zen so while he may not have got involved in the nitty-gritty he probably had a good deal of input on the decisions made during its design.

If anything I'd say he's probably going to be working on moving Intel away from their monolithic core design (is that the right word?) as Intel have essentially been stitching together what was a design from the over a decade ago based around a single core, i also say that because of how Zen is designed and the ARM multicore designs, and him having a lot to do with HyperTransport.

Obviously that also plays into your thought that he's going to be working on AI as (afaik) that depends on many cores working together.

[DanceswithUnix]

He was in charge of the team working on Zen so while he may not have got involved in the nitty-gritty he probably had a good deal of input on the decisions made during its design.

If anything I'd say he's probably going to be working on moving Intel away from their monolithic core design (is that the right word?) as Intel have essentially been stitching together what was a design from the over a decade ago based around a single core, i also say that because of how Zen is designed and the ARM multicore designs, and him having a lot to do with HyperTransport.

Obviously that also plays into your thought that he's going to be working on AI as (afaik) that depends on many cores working together.

Only non-monolithic core I can think of was Bulldozer which I believe was one of Jim's ideas. I doubt Intel will want to try that path

AI is closer to graphics in scale, a mass of multiply-accumulate operations. In that respect I think the scaling aspect should be well understood, just cut out all the rendering logic that a neural net doesn't need to cram more ALUs in.

[Corky34]

Yea i couldn't think of the right word to describe it as all i kept picturing was the big black monolith from 2001.

It wasn't so much the scale side of the equation i was thinking of, as you say that's well understood in graphics and compute cards, it's more the Zen type design of taking "an" core that deals with x86-x64 instruction sets and scaling that up to work with many more cores and have them all working as efficiently as possible.

If i understand correctly with GPU's and compute only situations you're working with fairly well defined timings, i.e a single MAC does X amount of multiply-accumulate operations per clock whereas "an" core designed to deal with x86-x64 instruction can be more 'random' based on what their running.

Basically i think they hired Keller to design something similar to how Zen was designed to be used in everything from low power single core designs all the way up to monster multicore server chips, Intel's current philosophy of stitching increasing numbers of ring buses together only take them so far before it starts to cause problems so they need another way of doing things.

[DanceswithUnix]

Yea i couldn't think of the right word to describe it as all i kept picturing was the big black monolith from 2001.

It wasn't so much the scale side of the equation i was thinking of, as you say that's well understood in graphics and compute cards, it's more the Zen type design of taking "an" core that deals with x86-x64 instruction sets and scaling that up to work with many more cores and have them all working as efficiently as possible.

If i understand correctly with GPU's and compute only situations you're working with fairly well defined timings, i.e a single MAC does X amount of multiply-accumulate operations per clock whereas "an" core designed to deal with x86-x64 instruction can be more 'random' based on what their running.

Basically i think they hired Keller to design something similar to how Zen was designed to be used in everything from low power single core designs all the way up to monster multicore server chips, Intel's current philosophy of stitching increasing numbers of ring buses together only take them so far before it starts to cause problems so they need another way of doing things.

Ah, so you were thinking more fabric than cores.

Intel have come up with their own take on hypertransport in the past, as well as their own version of ring-bus. I'm sure they can knock-off AMD's current fabric without Jim's help

Intel do have quite a few CPU cores though atm, though I don't know how may are in active development. The usual pentium to i7 range have the main core, but then some Xeon chips have a variant with wider AVX width as if the normal core wasn't FP monster enough. Then you get the Atom cores, the variation of Atom cores used for the Xeon-Phi compute cluster products (wide AVX, 4 threads per core), and then there is the attempted IoT 386 core that was never going to fly against ARM let alone RISC-V.

You get a lot of cores on a Xeon-Phi, seems they use https://en.wikipedia.org/wiki/Omni-Path not that I have seen any details on what that actually does.

[Corky34]

Ah, so you were thinking more fabric than cores.

Sort of, it's probably easier if i quote directly from an article on Semiconductor Engineering that talks about the problems the industry is facing in the rollout of these leading edge nodes.

An emerging trend here is the concept of a multi-layer chip where the base layer, which may contain the I/Os and some peripheral devices actually existing in 28nm, and then all the different computes, all the things that you’re pushing performance for actually exists on a separate layer,” Mohandass said. “Perhaps that’s on 16nm or 7nm. Although it may be referred to in different ways, it needs some form of intelligence connecting it all together.”

Logically, it’s perhaps one big SoC but you partition it, he noted. “Another way to visualize it even now when there is a standard IP, people think about it as doing the divide and conquer. They say, ‘Here is my CPU subsystem. Here is my image subsystem. Here is my memory subsystem.’ You partition your design with different subsystems and you put it all together. What we’re seeing now is it’s still the same except for perhaps a couple of partitions that actually exist in a separate chip. It’s just put together in the same package. Obviously this requires a pretty sophisticated interconnect, but this multi-layer of chips is something that’s getting more and more popular with decreasing process nodes.

I guess that can be considered a fabric type of thing but i was thinking more along a Lego type design that allows different IP and node sizes to be interchangeable with each other, a sort of EMIB on steroids.

EDIT: If you're bored another article on Semiconductor Engineering talks about advanced packaging and their interconnects, i recon Jim has been brought on-board to work on that sort of thing.

[DanceswithUnix]

I guess that can be considered a fabric type of thing but i was thinking more along a Lego type design that allows different IP and node sizes to be interchangeable with each other, a sort of EMIB on steroids.

Ah right, now I get you. I would expect that to be a tools/process issue more than anything else. Top metal layers are already on a much different pitch to the logic layers, but beyond that there is a push to cut down the amount of multi-patterning required. I think we already get that to some degree, the superbuffers that connect logic to the outside world via pads involve big transistors and big pads to connect to pins. But the likes of Jim will just see that as another tool so you can say "make that fast" vs "make that cheap".

[Corky34]

It is a tools/process issue but it's also a component problem, trying to get different IP that maybe using different levels of abstraction and different speeds all working efficiently is a bit of a mishmash currently, from that other article.

Trying to utilize off-the-shelf components for a single-chip solution can cause its own set of issues. “One of the problems we’ve been seeing in big SoCs is that companies are trying to glue everything together and the IP models are at different levels of abstractions and different speeds,” said Kurt Shuler, vice president of marketing at ArterisIP. “That requires you to shim and hack the interconnect model to get it to work. Even then, because of the ancestry of the models, they weren’t developed for pins or TCM (tightly coupled memory) interfaces, or they are cycle-accurate or approximately timed or loosely timed. So we’re seeing things that were not developed on a large scale. They were developed as a point problem.

That's what i believe Intel have been doing for years and while it works it's not ideal, even more so as node sizes fall and flaws become more likely.

[DanceswithUnix]

That's what i believe Intel have been doing for years and while it works it's not ideal, even more so as node sizes fall and flaws become more likely.

Nah, I don't think that is them as Intel do pretty much everything in-house and will maintain good consistency in design process.

Most companies don't do that. You get some logic designed in-house, buy in a hard cell with a couple of ARM cores, add some SerDes channels from someone else and maybe add in a hardware TCP/IP implementation from someone else. RAM controllers are hard to do so you buy that in too. You then get to try and mix all that together.

[Corky34]

Hm, I'm not so sure.

I accept that Intel do pretty much everything in house but because of the massive rise in fabrication rules as processor nodes shrunk that good consistency in the design process has (IMO) gone out the window, or is very close to it as shown by them struggling to get production of 10nm to acceptable levels.

I understand what you're saying about picking parts off the shelf and essentially throwing them together but that's pretty inefficient as you sort of have to bodge them together, that's why AMD are basing everything around IF, they don't have to worry about incompatible memory controllers, GPU/CPU cores, Network IP, or anything else they may wish to construct as all their parts are designed to work with IF regardless of what else is connected to it.