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And it has scheduled its move to 5nm mass production for the end of 2019 or early 2020.
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And it has scheduled its move to 5nm mass production for the end of 2019 or early 2020.
Looks likely to be the end of Intel's process lead that they've had for umpteen years.
A few on the cusp of 7nm. Don't think Samsung are too far behind either
That depends on the actual node densities though, Samsung 10nm node density was 51.82, TSMC 10nm node density was 52.51. Then you have Intel 10nm node density at 100.76. Not all processes are the same or equal.Quote:
Originally Posted by Man-In-A-Teapot
https://fuse.wikichip.org/wp-content...nm-initial.png
Agreed, though it has to be said that Intel's matured 10nm should be similar to the other fabs on 7nm, still their lead is gone.Quote:
Originally Posted by Man-In-A-Teapot
Not to say that you're wrong or anything, but I don't like the numbers on this graph, looking at Intel's actual 10nm numbers I'm calling BS.Quote:
Originally Posted by Iota
If it was estimated I'd say maybe, because take the 10nm low power i3-8121U they've just released, its not even up to scratch with their current 14+++++ or whatever their on now.
Eventually their 10nm process will hopefully get to where it's estimated to be, but the actual 10nm is currently below their current 14nm process albeit very matured 14nm.
Though I understand that the 7nm and 10nm would be the same once all the issues of current 10nm is resolved, i'd wager that current 7nm are leagues ahead of current 10nm.
And with 7nm on mass production Intel will need to sort out their stuff fast.
Though it can be argued that I've got little proof to show for 7nm, but that i3-8121U shows us enough to start thinking, while the 7nm process are showing crazy scaling compared to GF's 14nm (which can also be argued isn't Intel's 14nm) ,but either way 7nm will be better than Intel's leading 14nm which in turn places it firmly ahead of Intel's current 10nm.
On the last note I'm probably just reading/understanding the graph wrong, because the 14++ also doesn't make sense. (is lower better and if so why is the 7nm/10nm way up there?)
"The first chips out of the plant will be orders from companies wanting to provide next generation AI, GPU and cryptocurrency solutions"
1180 on 7nm then? if so that will be crazy fast.
Depends on what we're measuring, if it's transistor (FinFet) size then 7nm is slightly bigger than Intel's 10nm, i can't remember if it was Samsung, GloFlo, or TSMC but their FinFET's are few nm bigger, comparing size is pretty meaningless WRT FinFET, it's like trying to use road measurements for buildings.Quote:
Originally Posted by KN1GHT
Looks like Samsungs 7nm EUV is going to be late this year or early next. That *should* be a big thing with the first mass produced EUV process which brings some huge benefits
I think the thing to take away from the graph, is that the process name "10nm", "7nm" is just the commercial name and isn't an indicator of gate length, pitch etc. That's the way I understand it anyway, source linked below from where that graph came from.Quote:
Originally Posted by KN1GHT
https://en.wikichip.org/wiki/7_nm_lithography_process
https://en.wikichip.org/wiki/10_nm_l..._process#Intel
We have already seen a picture of the first 7NM GPU:Quote:
Originally Posted by Platinum
https://www.anandtech.com/show/12910...-shipping-2018
EUV is an attempt at cost reduction by not requiring multi-patterning. So far it has had such bad downsides that multi-patterning is actually cheaper. If they can fix that, great, but it won't make *better* parts and to start with it probably will be on cost parity with the old process so I don't expect to see cheaper chips either.Quote:
Originally Posted by 3dcandy
Judging a process by its transistor density alone is like judging an engine based on its capacity alone. For starters, the "industry" can't even agree on how to measure how many transistors a chip has.Quote:
Originally Posted by Iota
An example: The density of TSMC 20nm and 16nm is identical, yet one clocks better at the same power or has lower power usage at the same clocks.
Based on the last time I bothered to look at the details, IIRC TSMC 7nm should outperform Intel 10nm.
Density affects the number of dies per wafer, however if the yield is rubbish, there is no cost saving. Thus measuring a process by density alone is useless.