Intel Comet Lake-S Desktop CPUs rumoured to sport up to 10 cores

[nobodyspecial]

oops, meant Intel $200 or less in previous post. Close enough rofl. Point was ridiculous profits on all HEDT coming from those 4 models on same silicon. Heck might be cheaper now that I think about that fact and selling for $434-1723 (6950x on down), all from the same die.
https://www.anandtech.com/show/10337/the-intel-broadwell-e-review-core-i7-6950x-6900k-6850k-and-6800k-tested-up-to-10-cores
All based on 10core. Just an example.

[nobodyspecial]

https://wccftech.com/intel-broadwell-e-core-i7-6950x-launch/
The lcc die is 246. My mistake I'm talking the hcc as anand reviewed (IIRC ~450+, too lazy to read more at this point).
https://en.wikichip.org/wiki/intel/microarchitectures/broadwell_(client)
There, 456 and the prices that go with those are just stupid along with the margins. It, and it's ilk are why DC segment is bringing in 6B a quarter now. Silicon doesn't cost much for the gains in margins clearly.

[nobodyspecial]

Vega 64/56 are 486 mm2. So taking it further, 1/2 cu's ~246. So what is that at 7nm at 40% silicon savings? 147mm^2? Roughly. So together with cpu side, ~250mm^2 if 6 core right (assuming 100-110 on cpu side at 7nm)? Doable.

Again 14nm 2400g from AMD is 209mm^2 for $169 at launch. 250mm^2 ($200 price without mem?) could easily be done with GDDR5x 4-8GB from $250-400 as noted before (they'd be making money on the mem side...LOL). Math might be off by a bit either way, but I think I'm pretty close here. Yeah, I'm convinced AMD needs to make one Take my money AMD They'd make a killing on margins on the higher models clearly compared to their apu/console junk. Quit chasing dirt poor people AMD. Make something we WANT. The 2400g just wasn't good enough, while good 1080p is ripe for htpc gaming and within range of most buyers. Jeez, I was excited enough to keep doing math at 6am (simple build too BTW...No cards, etc)...ROFL. TSMC should be pretty good at 7nm by now after apple A12. They've been doing volume since April.

https://www.anandtech.com/show/13445/tsmc-first-7nm-euv-chips-taped-out-5nm-risk-in-q2
If I'm off a bit, we should be able to easily get this with 7nm 2nd gen before 2019's out if they're not able to do it already. Anandtech says 20% more transistors for 2nd gen and 8% lower power (6-12 I guess), so if my numbers are off above here, you can do it at gen2 next year correct? NP! If prices aren't right here, they will be at gen2.

TSMC taped out 10 customers in EARLY 2017, and we got iphone A12 sept2018. They are only doing 4 not so important layers of EUV to speed up the cycle here, so I'm thinking if they can't do it with 7nm finfet, they can with 2nd gen before xmas at 7nm finfet+ (the euv gen1 I guess). They are really just using it to learn, but still improving on 1st gen while doing it. BRING IT. ON a side note, Intel better get their butts in gear. TSMC is on a march here. 5nm in 2020? Intel will barely be getting to mass production of 10nm then...Good grief. I think AMD is getting a few cpu buys from my family next year and again 2020...LOL. I don't see how they could screw this up vs. Intel for a while at least. If it's 2nd gen 7nm AMD from TSMC vs. Intel 10nm if the figures are anywhere near correct, I'm in for AMD multiple times as long as they match Intel prices (not sure how much I'd go above, but at or below I'm in). Perf is already a win in apps (can't wait for 7nm handbrake baby!), and all 7nm should make games a go for me too. Hopefully they'll sell me a few HTPC chips too as I could use 1-2 of those (parents need one too, so 3). Heck I'd take them with 4-8GB GDDR5 even but would rather have GDDR5x I'm done, need some sleep, but thanks for making me excited edmundhonda.

[Tabbykatze]

Jesus christ man, can't you edit your post. It's not even a double post, mega quad post.

Then again, it is nobodyspecial so just gloss over the verbal diarrhoea because I tried reading it and I'm not sure even what points he is trying to make.

[DanceswithUnix]

because I tried reading it and I'm not sure even what points he is trying to make.

Yeah, I skimmed some bits of it. If anyone spots something insightful let me know.

All that talk of APUs, I presume AMD with their chiplet design will have Vega or similar chiplets as well as CPU for making an APU device. If they want to use HBM memory on something targetting 1080p at a budget, I expect 2GB would be a better option. It can still lean on system memory if you need more like a traditional APU.

[Tabbykatze]

Yeah, I skimmed some bits of it. If anyone spots something insightful let me know.

All that talk of APUs, I presume AMD with their chiplet design will have Vega or similar chiplets as well as CPU for making an APU device. If they want to use HBM memory on something targetting 1080p at a budget, I expect 2GB would be a better option. It can still lean on system memory if you need more like a traditional APU.

I think APUs using the infinity fabric with CPU and GPU chiplets will be a very logical step and could cause a turnaround in the APU market.

[DanceswithUnix]

I think APUs using the infinity fabric with CPU and GPU chiplets will be a very logical step and could cause a turnaround in the APU market.

Creates more questions though.

Could you crossfire chiplets?
Would you scale memory bandwidth by adding an HBM stack to each graphics chiplet?

[Corky34]

I guess it would use AMD's hybrid graphics if it was on the same package, IIRC it's the same sort of thing but allows IGPs to be paired with discreet stuff.

[Tabbykatze]

Creates more questions though.

Could you crossfire chiplets?
Would you scale memory bandwidth by adding an HBM stack to each graphics chiplet?

Crossfire chiplets, imagine the possibilities for on die vector and Deep learning processing by having an infinity fabric chiplet for AI with its own cores and memory directly attached to the CPU chiplets. Probably expensive and crazy talk but that could be a big thing. I think this chiplets design is so versatile and just doing CPU chiplets is the tip of the iceberg. IIRC in the Zen 2 EPYC showcase, the GPUs could directly communicate on IF to the CPU? I may be wrong and my google fu isn't up to snuff right now.

[DanceswithUnix]

I guess it would use AMD's hybrid graphics if it was on the same package, IIRC it's the same sort of thing but allows IGPs to be paired with discreet stuff.

I meant two or more GPU chiplets in crossfire, not a chiplet and external graphics.

AMD could do with a proper tensor core as well, to create AI chiplets and move all that 16 bit crud off our gaming GPUs.

[Corky34]

I kind'a though that's what you meant but couldn't workout if that would really be crossfire or if it's even something they'd do, i can't think of a reason to put two small Vega 10's, for example, on a substrate when you could just put a single Vega 20 on it.

Also i couldn't decide if two GPU chiplets on a substrate would really be crossfire as (iirc) they'd be using the IFOP data fabric so would, could, might they appear as a one GPU.

[Tabbykatze]

Well the new Vega processors with the infinity fabric fingers can operate as an up to 5 way Hive which allows direct memory to memory and core to core communications which could theoretically allow the system to operate as one whole rather than the sum of parts. One IF master and the others attached are slave processors for increased processing perf?

[DanceswithUnix]

I kind'a though that's what you meant but couldn't workout if that would really be crossfire or if it's even something they'd do, i can't think of a reason to put two small Vega 10's, for example, on a substrate when you could just put a single Vega 20 on it.

You could also ask why they would only put a few CPU cores in a chiplet. If they can fit Vega 20 into a single chiplet, then a pair of chiplets would be quite powerful

[Corky34]

You could also ask why they would only put a few CPU cores in a chiplet. If they can fit Vega 20 into a single chiplet, then a pair of chiplets would be quite powerful

Because that's the optimal layout for a multi-core CPU layout, any more than four mean data from some cores has to travel further to reach an exit point. That doesn't apply to GPU as they stream data through pipelines, one's scalar based and the other's vector.

[Tabbykatze]

Because that's the optimal layout for a multi-core CPU layout, any more than four mean data from some cores has to travel further to reach an exit point. That doesn't apply to GPU as they stream data through pipelines, one's scalar based and the other's vector.

Not sure that's quite true, putting smaller amounts of cores in a chiplet increases yields. The distances between core, chiplet and I/O can all be made the same relative distance on the tracings so therefore you would not lose or diminish bandwidth over distance.

[Corky34]

Apologies if that came across wrong, when i say per chiplet i mean per silicon die, as in loads of four core dies/chiplets can be put on a single substrate, fewer than four would increase yields but comes with the disadvantage of having to connect more dies together.