Goddamit I'm trying not to spend more money but your arguments are so well form it is like a spear through my wallet.
Well...4GB is on pre-order is suppose...
I have been using a Pi Model B with 256 mem for a few years and it runs Pi Hole well. It does not slow down your network or your internet access. It is only the DNS requests that are being processed by the Pi. Your downloads, for instance, do not go through the Rpis ethernet port.
Apologies, I wasn't clear. I've had a Pi2 model B running Pi-hole for a couple of years, I'm aware the network traffic just for doing DNS is minimal enough not to saturate the ethernet.
I'm saying I'd like the Pi to double up as a hardware firewall for my whole network. To do that all the internet traffic will need to run through it and that will require more bandwidth than previous Pis could handle.
The new one seems ideal for that.
I think in this case it is just that division is usually a rarely used instruction so ARM didn't waste too much silicon area on it. It's self fulfilling too, there is an old compiler trick to try and replace divides with multiplies because multiplies are always faster, and when people pull tricks like that it makes spending transistor budget on the divider less appealing. Then there is the TDP advantage of the 8300 which gives it double the clock speed.
OTOH, Intel make mahoosive cores and wouldn't blink at implementing very fast dividers, though even Intel only implement one of them for integer (Coffee Lake only has a divider on port 0. yeah I looked it up: https://en.wikichip.org/wiki/intel/m...es/coffee_lake )
It Ars had done their graph against an Atom chip, that would have seemed a more reasonable match.
Last edited by DanceswithUnix; 26-06-2019 at 07:44 AM.
aidanjt (26-06-2019),watercooled (26-06-2019)
I did originally mention a hardware divider in my post before I edited it out - I wasn't sure if that would have applied here, but I do remember hearing about inclusion/omission of the dividers around the AMD Stars cores IIRC? Something like the original K10 core (e.g. Thuban) didn't have them but the version used in Llano did.
If Llano had an upgraded divider, I never noticed
ISTR it is one of those cases where you trade off transistors used against how many bits per clock cycle it can work out, so there are various levels.
Interesting tables here if you search for idiv 32 or 64 bit you can see how the latency improves over the generations: https://www.agner.org/optimize/instruction_tables.pdf
But performance only improves for software that uses the divide instruction (Amdahl's law), for other code it is just a waste of area which hurts clock speed!
Edit: I mentioned A72 vs Atom above, but it sounds like the Llano divider was used in the Jaguar as well so it must have been area and power effective.
Pi Hut have apparently sold out of 4GB models.
There are currently 1 users browsing this thread. (0 members and 1 guests)