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"We're already in business negotiations with customers on N4," said TSMC's Mark Liu.
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Read more.Quote:
"We're already in business negotiations with customers on N4," said TSMC's Mark Liu.
Samsung claims 0.65x the area for 3nm compared to their 7nm so the numbers are purely fluff. If it was real, 0.65x would have been achieved with a 5.5nm process.
4nm in this case is similar to TSMC's 12nm, which is a modification of their 14nm, and is akin to Intel's plusses. Even 14nm is not a full shrink of 10nm. 14nm vs 28nm is more like 2.5x rather than 4x, and its similar for 7nm vs 14nm.
One "generation" focuses on transistor density(like TSMC 20nm, and 10nm did) and the other "generation" focuses on performance(like TSMC 14nm, and 7nm).
So if it looks like we're progressing faster than ever, we're not. Pre-28nm each true shrink brought both full density and performance gains.
Not really.. the Node size is referenced to the size a single transistor can be made, there is more than transistors in a CPU die capacitors/diodes/inductors/fuses. then there is required EMR distancing think of it as social distancing in in a CPU so one side of a given circuit does not pick up electrical signals from another and cause interference. so real life scaling does not follow the Nm node size that a transistor can be size wise.
Node size hasn't directly correlated with transistor size for ages - it's all branding these days, there's no 7 nm features in 7 nm chipsQuote:
Originally Posted by PMMEASURES
[QUOTE=Xlucine;1163601]Indeed, in a round about way that is what I was implying, essentially its the etch/cut size you can have a transistor at the size but you also have to have connecting traces to ..so bye bye to anything that could resemble the node size.Quote:
Originally Posted by PMMEASURES