IBM takes the wraps off its 7nm Power10 processor

[HEXUS]

It is 3x more efficient than the Power9. First Power10 systems expected H2 2021.

Read more.

[3dcandy]

up to 15 smt8 cores yet the die shot clearly has 16....

[CAT-THE-FIFTH]

up to 15 smt8 cores yet the die shot clearly has 16....

Might be disabled for yield purposes? Made by Samsung too on 7NM.

[kompukare]

up to 15 smt8 cores yet the die shot clearly has 16....

Guess they don't expect perfect yields?

[3dcandy]

Well yes - but that's a huge amount lopped off for yields...
Surely they'd be fusing off poor cores on the lower end offerings instead to make a product stack like every other manufacturer does?

[edmundhonda]

Well yes - but that's a huge amount lopped off for yields...
Surely they'd be fusing off poor cores on the lower end offerings instead to make a product stack like every other manufacturer does?

Samsung's 7nm hasn't been used on anything more advanced than a mobile SoC, has it? It might just be that the yields at this size (602mm2 is enormous) and complexity are notably poor.

[DanceswithUnix]

Surely they'd be fusing off poor cores on the lower end offerings instead to make a product stack like every other manufacturer does?

I don't think IBM really do low end offerings, the machines I have used started around the half a million quid mark and run *lots* of virtual machines so would be likely housing a few of these processors. Then there is the whole thing of shipping with more cores than the customer ordered and allowing them to buy an upgrade licence if their usage increases.

[scaryjim]

Well yes - but that's a huge amount lopped off for yields...

Not that unusual, given we're talking 16 core blocks with 8 threads per core it's presumably a large and complex chip. I suspect an extremely minor defect in any single core block could render it sufficiently unstable to need fusing off, and almost the entire chip is core blocks or associated cache...

[3dcandy]

Not that unusual, given we're talking 16 core blocks with 8 threads per core it's presumably a large and complex chip. I suspect an extremely minor defect in any single core block could render it sufficiently unstable to need fusing off, and almost the entire chip is core blocks or associated cache...

Well surely in that case you'd modify the design to mitigate that. Extremely wasteful otherwise but hey maybe that's just me...

[DanceswithUnix]

Well surely in that case you'd modify the design to mitigate that. Extremely wasteful otherwise but hey maybe that's just me...

It is just the execution units that are the problem.

If you have a defect in the L1 or L2 cache that make up a lot of the area, then there will be spare lines that they can swap in to repair.

You can't do spare bits of the main execution path though, as that would make them larger so the longer wire lengths would lead to slower clock speeds. Better to just allow for one bad core, and if all the cores work you can improve performance by killing off the weakest.

[kompukare]

It is just the execution units that are the problem.

If you have a defect in the L1 or L2 cache that make up a lot of the area, then there will be spare lines that they can swap in to repair.

You can't do spare bits of the main execution path though, as that would make them larger so the longer wire lengths would lead to slower clock speeds. Better to just allow for one bad core, and if all the cores work you can improve performance by killing off the weakest.

Yes, while we enthusiasts keep talking about golden samples or getting very lucky in the die lottery, on such big chips the likelihood is that the cores will be far from equal. So they've probably used less than 1/16 die space not only to improve yields but also binning.

[Rubarb]

7nm wow !......... thats like what intels profit is going to be if it doesn't pull its finger out soon