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Between then and now we will see N5, N5P, and N4. And TSMC intros 3DFabric package tech.
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Between then and now we will see N5, N5P, and N4. And TSMC intros 3DFabric package tech.
I thought going down this small was supposed to hit theoretical limits soon (or at least that was Intel said when they abandoned Moore's law a few years ago). Have I missed some break through? Aren't we getting to the stage where gates are just a few atoms wide now?
A quick Google says Silicon atoms are 0.2nm, so yeah you don't get a lot of atoms across a gate width.Quote:
Originally Posted by cheesemp
Lots of fins to get fets to actually switch off has helped, and EUV lithography to help draw such small features. But I have to wonder how close we are to the end of the road here.
This is why silicon makers are looking so hard at stacking/joining die in a package to keep making more powerful devices.
So what is Intel going to do?
"Assuming all goes to plan, we have 2022 with 7+, then 2023 with 7++ and another new process node, believed to be 5nm. This is expected to be the inflection point with TSMC’s 3nm in terms of density, which could suggest that this is where GAA technology is likely to be.Quote:
Originally Posted by QuorTek
Going beyond that, 2024 is 5+, then 2025 is 5++ and 3nm. If I were a betting man, and I predicted that Intel’s timeline over the course of five years might slip the best part of 6-12 months, then 2025 might still be in the 5nm / 5+ era. So with Dr. Mayberry saying within 5 years for high volume, the smart money would be GAA coming at 5nm, in 2023-2024."
https://www.anandtech.com/show/15865...-in-five-years
I'm just surprised how consistent TSMC is in their node development.
I'm only parroting Mr Keller but he said a Fin on a modern transistor is around 120 atoms and quantum effects start at around 10 atoms so it seems we've got a way to go, physically speaking. (If the time stamp doesn't work it's around the 34min mark)Quote:
Originally Posted by DanceswithUnix