Between what Tabbykatze and yourself have said now I'm totally lost, the first thing i knew about the BAR was having a video GN did about this release on in the background so i defiantly wasn't paying much attention, i can hear my teacher now shouting out for the pupils at the back to pay more attention.
I think we've got a great big ball of wires though, i thought CCIX was for cache coherence between CPU's and an 'other' cache, something this (AFAICT) isn't because it seems to be about how much of the system RAM can be addressed at a time, and I'm not sure it's about what your talking about either DwU as you seem to be describing the address space that PCI(e) register themselves at and not the other register that PCI(e) uses when it's addressing data stored in RAM.
EDIT: You seem to be talking about the PCI configuration space whereas "Smart Access Memory" seems to relate to the reserved address space in RAM for when something needs to send data to the device.
Last edited by Corky34; 30-10-2020 at 10:41 AM.
This feature allows the CPU to just simply access the whole of the GPU memory as one simple linear lump, rather than having to go through small windows into the ram.
How you access the memory on any PCI(e) card is set up through the PCI configuration space, using the base address registers.
The thing I am confused about is that this shouldn't be hard. I assume the difficulty would be in some older BIOS implementations having expectations on how a video card is set up that it potentially breaks, so perhaps there is some finesse in the configuration for backwards compatibility. That might explain why they claim it only works on 500 series motherboards with 5000 series CPUs. That is odd, when 5000 series CPUs share an IO die with 3000 series, and the 4000 series APUs are more recent.
Edit: I've had a bit of a refresher recently reading about BAR registers in context of the raspberry pi compute module and people trying to get video cards working on the PCIe x1 interface of the breakout board. The first hurdle was the Pi configuration only allowed a piddly 64MB of address space to be mapped by the PCIe card. Seems they've got past that now, and into other problems. Wonder if their hacks will be good enough to map a 16GB vram, though I suspect a 6800 GPU might be a tad bottlenecked by that arm SOC
Corky34 (30-10-2020),Tabbykatze (30-10-2020)
AMD has supplied some benchmarks:
https://www.amd.com/en/gaming/graphi...ing-benchmarks
Yeah saw those a few hours ago, if they hold water then team red are back in the game.
I do like in forza 4 1440p even the bottom 6800 kick 3090 ass
For me Nvidia is for RTX and always will be .
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