On the other hand, Samsung had no problems meeting demand for GT1030 and GT1050/Ti with their 14nm.
And even with the new 8nm products, there were stories that at least for GA102 (3080 and 3090) GDDR6X supply is major problem too.
Also GA102 is a 600mm²+ product which they seem to have decided to run past the perf/watt sweetspot of Samsung's 8nm. Guess time will tell: if they launch a GA102 3070 Ti with plentiful supply it probably means that 600mm²+ at the speed of 3080 and 3090 was pushing it.
As for AMD and Samsung Semi: well we have no idea what size chips AMD intend to fab there. Zen3 CCDs at under 100mm² would be totally different than trying to fab Navi21 (which is already 520mm² with TSMC's 7nm and would be close to 600mm² on Samsung's 8nm going by the transistors/size of GA102 vs the existing Navi).
Also, porting / redesigning (which is a more accurate description of the work which would required to move a design from TSMC's 7nm to Samsung's 8nm) probably takes a year or so so unless AMD started this work ages ago (and like I said in the PS5 comment, do AMD even have enough engineering resources to have begun this already while already taping out three consoles chips, Zen3 in both CCD and APU format - I think not) this is far more likely to be a Samsung post-8nm node.
From wafer requirement calculations, the consoles are taking up to 80% of AMD's TSMC allocation so it makes the most sense to port those and with at least the PS5 chip already running past the sweetspot of TSMC's 7nm node, porting it to a worse node (Samsung's 8nm) would be impossible as a console is fixed (that is they can't 'simply' redesign it so the GPU runs slower but wider).