Read more.Quote:
Touts 75 per cent reduced power consumption compared to iso-perf 7nm chips.
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Read more.Quote:
Touts 75 per cent reduced power consumption compared to iso-perf 7nm chips.
In those pictures I cant see 2nm dimensioning.
yeah it smells wrong this
Why compare to 7nm (and without specifying which foundry's 7nm even that's not too meaningful)? 5nm chips are already being produced, and TSMC's N5P is 40% more power efficient than its N7 process. 3nm at TSMC will enter risk production this year, while this 2nm process is just a research project, and this 2nm process will not be that much denser than TSMC's 3nm (according figures in the Anandtech news article on this).
All in all, nice, but seems more hype than anything else.
Really, why's that?Quote:
Originally Posted by rabidmunkee
7nm is in mass production for multiple businesses from both TSMC and Samsung (very similar processes), 5nm is not as it's just for Apple.Quote:
Originally Posted by ET3D
So Intel invented 7 nm, but they still do not produce on it ( or have i missed something )
Of course skipping a few nodes and go strait to 2 nm, thats not bad, but really i need to see production samples in my hand before i put down that piece of equipment and clap my hands.
I think people may be kinda missing the point of the press release - they are announcing a cutting-edge node in development, not something you should expect to see in a product you buy tomorrow. It's common practice to talk about future nodes, and it's important to remember that node names can't necessarily be compared between companies. TCMC 7nm is not the same as Samsung 7nm for example, and Intel 10nm is not the same as TSMC 10nm.
Aside from feature size, this is also a novel transistor design, along the lines of how FinFETs were introduced after planar transistors.
Regarding the comparison to 7nm, it's just as valid as any. Foundries may compare to their prior nodes in mass production, but IBM in this case are better off comparing to a widely-available and well-understood node.
There was no "inventing" 7nm, ASML and others like IBM or university researchers will create a method on how to shrink transistor size.Quote:
Originally Posted by Gentle Viking
Like Planar FETs were invented decades upon decades ago and were iterated over with variations and methods that made them small. The "first" FinFET was actually fabricated in a Hitachi lab.
7nm is just a moniker for an arbitrary sizing, 7nm Intel != TSMC 7nm and I'm amazed how people still just don't get that.
Anandtech have produced a table including transistor density in their article on the subject https://www.anandtech.com/show/16656...first-2nm-chip
Transistor density still isn't the whole story, but it's an actual comparison point vs just a naming scheme, which is all 7nm etc are nowadays.
There was a really interesting video on Dr Cutress's Youtube channel about Moore's law and the effect this has. There was a snipped of a lady going through the cost per tranny at different nodes but there was a far more interesting part. She said that power requirements for transistors was not decreasing linearly in proportion to size. The end result is that they have to turn large sections of core off to allow it to operate within the specified TDP. It may be common knowledge, but it was news to me.
Which in turn has led to immense power density, especially in high-clocked parts like desktop CPUs. And that means it gets quite difficult to cool the things, and even with soldered IHS it's common to see load temperatures in their 90s. Some people still get unreasonably hysterical over temperatures, but it's just how modern CPUs are intended to be.
We have seen some impressive advancements in terms of fine-grained clock and power gating recently too. It's more crucial on mobile processors for obvious reasons, but like you say even on desktop parts, it allows parts to be shut off to save TDP headroom more so than being an overall power consumption measure.
I wonder what will happen when we reach the end of Moore's Law.
We make die lower power, and stack them vertically. It is already happening with things like flash chips which ISTR are commonly stacked 96 die high.Quote:
Originally Posted by fend_oblivion
Perhaps, but comparing a newly developed process to the most common process rather than the state art is still pure hype. It's meant to sound impressive rather than show any real advancement. The end result is that it's misleading, and not of much value.Quote:
Originally Posted by Tabbykatze
Several companies will have 5nm chips produced this year and the next.
Flash chips are actually made with 96 layers of storage cells on a single die. You can find many nice SEM images at https://www.flashmemorysummit.com/Pr...202-1_Choe.pdf - mind you, all of them are cross sections of a single die, not a stack of dies.Quote:
Originally Posted by DanceswithUnix
Flash seems to be the only type of product that allows this kind of stacking, due to several reasons: acceptable power density, no need for many complex interconnect layers, and no need for best and fastest transistors. The best and fastest transistors (logic) can still only be made on the bottom layer, meaning on the substrate.
But you can see 12nm and 5nm dimensioning, and then there are some thin dark and light layers that you can estimate to be ~2mm thick. Those are passivation layers or something similar though, formed by deposition, not lithography. Still I'm amazed at that.Quote:
Originally Posted by lumireleon