Sony tipped to be preparing a PlayStation 5 Slim with 6nm APU

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The new console should be smaller, cheaper, and use less power.

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Read more.

That would keep AMD quite busy re-designing for 6nm.
Would hope Sony would spec with more redundancy or whatever is needed to actually meet their clock targets, as current rumours still point to Sony having to scrap lots of (otherwise working) dies to meet the current PS5's spec after Sony changed the clock targets so late in the development cycle.

Since Sony is expected to ship around 15 million PS5 per year or so, this will continue put huge strain on TSMC wafers - just 6nm rather 7nm wafers.

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Originally Posted by hexus

For a start N6 can achieve better yield and shorter production cycles compared to N7 technology

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First time I've seen this - if true that bodes well, I thought N7 was already pretty good.

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Originally Posted by kompukare

That would keep AMD quite busy re-designing for 6nm.

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erm, from the article:

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Secondly the design rules are fully compatible with N7

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so almost no design effort required on AMD's part, and I imagine the testing of new parts is split with Sony.

These will be the same starting wafers regardless of whether they hold a 6nm or 7nm design, so if the design becomes 18% more dense you get more chips per wafer, and then hopefully fewer chips rejected, so it could have quite an impact. If it didn't then Sony wouldn't stump up the cost of new masks, so they must see a long term cost saving which can only be gotten through getting more chips per wafer.

Hopefully won't just be a optical drive-less slim model and just a V2 with both options available. Maybe finally get one Christmas 2022 :)

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Originally Posted by DanceswithUnix

erm, from the article:



so almost no design effort required on AMD's part, and I imagine the testing of new parts is split with Sony.

These will be the same starting wafers regardless of whether they hold a 6nm or 7nm design, so if the design becomes 18% more dense you get more chips per wafer, and then hopefully fewer chips rejected, so it could have quite an impact. If it didn't then Sony wouldn't stump up the cost of new masks, so they must see a long term cost saving which can only be gotten through getting more chips per wafer.

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I forgot that TSMC's 6nm and the 7nm are meant to be so close.

Still, a quick port might not do anything for yields.

And, since we suspect that Sony's last minute change to clocks is the reason for poor yields, addressing that must be a high priority. Okay, not a lot of work - and after all AMD pushed out three consoles SoC, Zen3 and Renoir (plus others?) over the last year - so one new chip shouldn't be too hard.

Unless making sure more candidates can hit the wanted speed involves lots of work. While we don't even know which part of the SoC often cannot hit their clocks, it could be as simple as a minor part of the GPU. Or it could be every part of the SoC, we simply don't know.

Can't imagine this would facilitate a slim, maybe a "not quick as mahoosive"?

The not up to to snuff chips are being re-used - say Hexus for more details ;)

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Originally Posted by 3dcandy

The not up to to snuff chips are being re-used - say Hexus for more details ;)

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I did see those. But if they've shipped 8 million and if even only 5% are "couldn't quite meet the spec" chips, that's 400,000 chips. And that machne had the graphics disabled too. Very strange.

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Originally Posted by kompukare

Still, a quick port might not do anything for yields.

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A smaller die should improve yields for a given number of physical defects per wafer.

If the new process allows higher clocks (which they tend to), then that should improve performance margins and mean fewer rejected on performance grounds.

Seems an easy win to me :)

I have also seen on other websites that there is a backlash against the design....
Guess a quick change wouldn't harm them either!

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Originally Posted by DanceswithUnix

A smaller die should improve yields for a given number of physical defects per wafer.

If the new process allows higher clocks (which they tend to), then that should improve performance margins and mean fewer rejected on performance grounds.

Seems an easy win to me :)

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Sure, but part of the speculation about Sony, PS5 and yields is that the had far more unusable dies than Microsoft despite having the smaller die.

As both are on TSMC's 7nm, part of the speculation is that Sony's decision to push for higher clocks after the design was done is the reason.

Hence, we aren't necessarily talking about defects per wafer or even the normal definition of yields.

Rather, this is binning and it looks like for the PS5 they require only the better dies.

Problem is Sony aren't AMD or Nvidia and can't sell them as a PS5 slightly lite or whatever.

So they are possibly throwing perfectly functional dies away. Or not depending on where those 'AMD Cardinal' PCs with those 4700S and GDDR5 memory came from.

Using the exact same design rules on the PS5's existing SoC might not improve clock speed binning.

True, but if the problem was not getting enough chips to hit a particular frequency/volts target, then shrinking the node should improve that metric. On top of that you can get more chips out of a wafer *if* the waver defect doesn't change (though I don't know if you expect more defects towards the edge therefore you might hit more with a smaller process) then all other things being equal your yield increases too. Many assumptions there which makes me slightly suspicious that yield would actually increase, especially at the start of the production, but I am not a fab engineer so I have no real insight.

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Originally Posted by kalniel

Many assumptions there which makes me slightly suspicious that yield would actually increase, especially at the start of the production, but I am not a fab engineer so I have no real insight.

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Totally agree, but we have one extra bit of information: Sony, who so have access to all the right people, have decided to do this which will involve new setup and mask fees. So what are they getting out of this? I can only see cost reduction and volume improvements as drivers right now.

The only listed advantage I could find for N6 was 18% better density than N7. There was a vague mention of better performance on one slide, but without the usual proud marketing numbers to give any hint as to magnitude.

But here we are, being told there is a PS5 slim version. Now that can either be the same power consumption as before but with noisier cooling to keep the heat under control in a smaller case, or they have less heat. If they have less heat, then that says they need less volts to get the clock targets. Less volts says it isn't so close to the ragged edge as it was before, which sounds very good for yields.

An important thing to remember is N6 uses EUV. The N7 process the PS5 SoC is produced on does not as far as I know. The N7+ node does but that isn't what is being used unless I'm mistaken.

I think part of the reason N7+ was not used is partly due to a mix of reasons including EUV scanner availability, lack of pellicles and EUV die size limitations (which is why we have only really seen small mobile processors produced on EUV nodes, none of AMD's products. And likely the same story for Nvidia using Samsung 8nm, not their 7 node which is EUV).

Anyway, EUV could have an impact on yield and binning...