TSMC reckons intrachip cooling might become necessary soon

[Iota]

Wouldn't that also make the dies themselves larger?

It seems to be more of a case of finding a problem for a solution, than the other way around. Instead of 3D stacking why don't they just make larger dies, it's far easier to move heat away from a larger area than it is from a smaller one. Sure it'll mean larger sockets, but the benefits are they can adopt a much more forward looking approach instead of realising they're 3 pins short for what they want to do on the next product iteration. Make the socket for say, 3000 pins now, use the extra pins later on, instead of constantly changing sockets to increase the pin count. It'll make it far easier for end consumers buying cooling, as they wouldn't need to have new adapters etc or completely change their cooling setup.

[Corky34]

They're constantly trying to work out the best next best replacement material for Silicon and it keeps getting tossed around whether it should be Graphene, ground up leprechauns or cheese.

Cheese, defiantly cheese, preferably on toast.

[kalniel]

It seems to be more of a case of finding a problem for a solution, than the other way around. Instead of 3D stacking why don't they just make larger dies, it's far easier to move heat away from a larger area than it is from a smaller one. Sure it'll mean larger sockets, but the benefits are they can adopt a much more forward looking approach instead of realising they're 3 pins short for what they want to do on the next product iteration. Make the socket for say, 3000 pins now, use the extra pins later on, instead of constantly changing sockets to increase the pin count. It'll make it far easier for end consumers buying cooling, as they wouldn't need to have new adapters etc or completely change their cooling setup.

I don't think socket size has much correlation with die area - we seem to be getting smaller and smaller dies, yet larger and larger sockets.

[Tabbykatze]

It seems to be more of a case of finding a problem for a solution, than the other way around. Instead of 3D stacking why don't they just make larger dies, it's far easier to move heat away from a larger area than it is from a smaller one. Sure it'll mean larger sockets, but the benefits are they can adopt a much more forward looking approach instead of realising they're 3 pins short for what they want to do on the next product iteration. Make the socket for say, 3000 pins now, use the extra pins later on, instead of constantly changing sockets to increase the pin count. It'll make it far easier for end consumers buying cooling, as they wouldn't need to have new adapters etc or completely change their cooling setup.

That would make the cost to consumer problem worse!

Larger, more monolithic dies mean less can be produced per wafer and of those fewer per wafer you will have a higher defect density meaning less perfect/ideal dies and more faulty dies wasting silicon and driving up costs. Sure, it may be a bit easier to cool in the long run but not every part of the die is a hotspot generator so you will get heat crowding around specific areas (the cores) so unless the design spreads them out equally, you're back to square one (this is kind of a straw man comment, but it has been seen on intel monolithics).

There is a reason why all major silicon manufacturers are following AMD down the chiplet architecture as they're easier to manufacture, you can manufacture more while discarding less and in turn reduce costs overall which can be provided to the customer in the end.

The next step is to make smaller distributed logic functions like IO, ram controller etc and stack them so you're saving space and manufacturing/build area.

[bae85]

I bet they'll end up looking like the 'chip' from Terminator, little cubes linked by a substance...

[DanceswithUnix]

Wouldn't that also make the dies themselves larger?

You still need to seal it hermetically,have a reservoir,have a way to monitor liquid level,etc. Then will it integrate into existing fansink combinations,or need a specialist system? That sounds like added complexity,which means more cost.

If it is sealed then the device is the reservoir, much like a heatpipe. You know you have lost liquid if the temperature starts throttling

If it transfers the heat to the top of a heatspreader, then main cooling could look much like it does today.

I just want to see tiny little MEMS pumps integrated onto a cooling silicon layer, just coz tiny pumps sound cool!

[CAT-THE-FIFTH]

You guys seem very optimistic about the costs,but I can see the CPUs using this being very expensive because of the increased complexity. Remember,what happened with HBM?? Any cost reductions were swallowed up by packaging costs and complexities. It also makes me wonder about AMD chiplets too. AMD APUs might use more 7NM silicon,but the RRPs of the Ryzen 5 5600G and Ryzen 7 5700G look to be lower than their CPU equivalents,despite the latter using less than half the 7NM area in the chiplets. I do think at the higher end it saves a lot of problems,but it makes me wonder as you go lower down the stack,whether it's as cost effective. Nobody has looked into the additional costs of more complex chip packaging,which often needs moving the chips to factories in the rest of the world.

Remember,TSMC would need to build a dedicated packaging line to implement this kind of cooling solution,and that needs to be paid for. This is probably also another reason why TSMC wants to do this,ie,they can charge more and expand in-house chip packaging and finishing, as they are taking business away from its competitors who do handle packaging themselves(TSMC supplies the wafers and these companies package and finish the final chips). It locks you into using TSMC for more stages of chip production.

AMD used to do this in-house until it sold that part off in 2015:
https://www.guru3d.com/news-story/am...t-venture.html

There is a big difference between putting an IHS on top with some thermal compound and having to not only make the die larger,because you need incorporate channels,but also the fact the whole CPU package can't be sealed by normal methods. Then the added costs of making more layers on the CPU itself. This is why I said it had to be hermetically sealed,so nothing can get in and out,and remember when liquid gets hot,it expands and there is increased pressure. The liquid is going to be under very high pressure if natural circulation is to work. If you need to use pumps,then its a waste of time,because it makes more points of failure and even more additional complexity and cost.

I would also suspect,the IHS has to be made of a thinner but still physical strong material,as the thermal capacity of such a tiny volume of liquid is going to be small,and you would really need to pump that heat out quicker than normal methods. Its why you had improperly sealed heatpipes many years ago burst.

TSMC might be saying its "great" but again I can't see this as being cost effective for average consumer applications. If its 100% needed,I can't see very complex 3D stacked chips of this typereally entering,entry level and mainstream systems,be it smartphones or PCs,for many years more. Remember,this is on top of the greater costs of new nodes.

HBM,Optane,etc were all well received technologies but they put performance first,cost benefits second. Yet,inferior,but easier to implement technologies always win out.

Ultimately I don't see the technology being of any real use for most devices being made for the immediate future.

[DanceswithUnix]

You guys seem very optimistic about the costs,but I can see the CPUs using this being very expensive because of the increased complexity.

Think of the alternative. If you can't fit it in a single package, you fit it into two packages so now you have double the package cost. These things are usually aimed at laptops too, where fewer packages is a big plus.

[CAT-THE-FIFTH]

Think of the alternative. If you can't fit it in a single package, you fit it into two packages so now you have double the package cost. These things are usually aimed at laptops too, where fewer packages is a big plus.

The problem is the same arguments were used for HBM/HBM2 usage in laptops - it still ended up cheaper to use a larger PCB,mixed DDR/GDDR RAM,etc and engineer around it despite the extra power consumption. The same with consoles which even use an SOC,but used GDDR type RAM,despite the fact it means a larger PCB with more energy costs.HBM,and its associated packaging costs,and more finicky production steps made it less viable in such scenarios.

The issue is if the packaging costs and complexity are too high,it does not give you cost savings and more importantly.....its a production rate limiting step. Now think if this was implemented for every chip made in a smartphone,tablet or PC out there - it really does not seem viable ATM.

I can't see the costs of a stacked solution incorporating large dies,due to building in silicon channels,etc and needing hermetically sealed IHSes,etc as anything apart from increasing the bottomline of TSMC. This way any of the 3rd party companies,doing the packaging,won't be able to compete because TSMC can point out the chips will only work with their own in-house cooling solution. I really doubt TSMC is going to start licensing out the technical aspects of this so 3rd party packaging and finishing companies can implement their own solutions.

[DanceswithUnix]

I can't see the costs of a stacked solution incorporating large dies,due to building in silicon channels,etc

Why would channels make the die larger? They start off really thick with plenty of material on the back for you cut channels into, for stacking you often have to thin that down anyway so the top layer will have material to spare. Unless you think they would add channels on the side? You wouldn't do that, that's not where the heat is.

Edit: At this point die have been stacked for well over a decade, mainly flash and ram. This cooling comes across as a tad cocky to us, but they well might have the experience that it is actually pedestrian to them. Clearly test parts have been made, this isn't theory.

[CAT-THE-FIFTH]

Why would channels make the die larger? They start off really thick with plenty of material on the back for you cut channels into, for stacking you often have to thin that down anyway so the top layer will have material to spare. Unless you think they would add channels on the side? You wouldn't do that, that's not where the heat is.

If the normal stacking is already meaning a thinner die,then if they have to make it thicker again,than means you are using more sillicon than normal. Plus you still need to etch these things,so another layer of manufacture and complexity. Its going to cost more. TSMC is not going to eat costs for any of us.

Plus another issue is how cutting tons of channels under the chip,is going to make it physically weaker too because you are cutting out support material. Also,especially if you have a small volume of very hot,high pressure liquid going through it.

How long has this been tested for?? Days,weeks,months?? What was tested?? An actual fully fledged CPU?? Or some test die? What was the power output of said chip tested,etc??

There is a big difference between a proof of concept,which just needs to show it "works" and actually something useful working under diverse conditions in an actual realworld scenario.

Edit: At this point die have been stacked for well over a decade, mainly flash and ram. This cooling comes across as a tad cocky to us, but they well might have the experience that it is actually pedestrian to them. Clearly test parts have been made, this isn't theory.

Its not cocky,its a way to cut out competitors from packaging the TSMC made wafers,so they can do more of it in-house. This way you can lock TSMC into the whole process from wafer etching to final finishing and assembly. They want to overengineer a solution so you are forced to stay with them,and make sure competitors get screwed.

Yet,again test parts were made with HBM,etc and where did that lead to?? AMD were testing out stuff like this nearly a decade ago. Look at the predictions on tech forums,we would be having HBM for laptops and GPUs,because of smaller PCBs,lower power,etc. It went nowhere for a lot of consumer applications - just because it works in a lab,does not mean it makes sense for making billions of devices. How many "revolutionary" technologies have been talked about,but years and years later you don't see them in many consumer products.

Plus with stacked NAND/DRAM there is no liquid cooling involved,etc and companies making the RAM sticks and drives,just substituted it for the "planar" stuff they were using before. Once you need to start adapting whole parts of the process ,by trying to reinvent the wheel all the time,it just gets in the way. The fact is cost and availability is what has driven adoption of technologies forward. Its why we use X86 CPUs in Windows PCs,why ARM took the rest of the market and why VHS,DVD,etc won over "better" formats. None of them were the best,they were the most easily available or cost effective technologies at the time.

Look even on here and elsewhere about MRAM? Nearly a decade later its not used that much in consumer situations. Optane is the same.

MicroLED panels?? Those were demonstated nearly a decade ago. Lots on forums got excited about those. Only in 2020/2021 can you actually buy one,and they are expensive.

Even look at process node technologies?? SOI is superior to standardised bulk type technologies,but due to cost and complexity issues,SOI has fallen behind. No point if its better,if its harder to shrink the transistors down in the first place,or it costs more.

As much as stacking is the future,its like RT being the future too. Its an interesting experiment,but even then it costs more for CPUs and GPUs. Even AMD is only putting its "stacked" L3 cache on its highest end two consumer CPUs,and they will charge a premium for it. It won't be widespread in CPUs,GPUs in desktops,laptops,consoles,etc until the costs of packaging and cooling are reduced. Its why Intel Lakefield was a niche product - it cost too much. That is why I also think stacking will see more widespread use in high end smartphone SOCs,as the lower power demands,means cooling is less of an issue for the bottom layers. Even that will require costs to be low enough,so Apple and Samsung can keep their margins high.

Like I said many of you are way too optimistic with these things.

[Xlucine]

If the normal stacking is already meaning a thinner die,then if they have to make it thicker again,than means you are using more sillicon than normal. Plus you still need to etch these things,so another layer of manufacture and complexity. Its going to cost more. TSMC is not going to eat costs for any of us.

For stacking you don't use thinner wafers - they deposit the circuits on a normal wafer, and then grind off the back until it's the desired thickness

[Tabbykatze]

Cat, I do have to ask, what is your point?

Is it simply to state we shouldn't be excited for something that may or may not actually come to fruition in the near future or may consequentially increase prices for the consumer...?

[DanceswithUnix]

SOI is superior to standardised bulk type technologies,but due to cost and complexity issues,SOI has fallen behind.

SOI was a way to reduce leakage, and finfets go about that in a different way. The world moves on...

Still, your comments about HBM are quite apt here. If this works out too expensive or unreliable then it won't take off. Simple as that. In the meantime, it is an interesting technique which I'm sure is still actively evolving.

I'm sure most of the arguments that this is too hard and expensive could have once be made about chiplets. Or flip-chip. Or ...

[Corky34]

There's probably a reason but why don't they transport the heat to the surface (heatspreader) using something like copper (or other thermal conductive material) pillars, sort of like how you sink foundations into the ground, like this but upside-down and the transistors and all that gubbins surrounding the pins.

They lay down copper interconnects and use through silicon vias so i wouldn't have thought having 50nm (or whatever) wires to conduct the heat away wouldn't be much extra work.

[Tabbykatze]

There's probably a reason but why don't they transport the heat to the surface (heatspreader) using something like copper (or other thermal conductive material) pillars, sort of like how you sink foundations into the ground, like this but upside-down and the transistors and all that gubbins surrounding the pins.

They lay down copper interconnects and use through silicon vias so i wouldn't have thought having 50nm (or whatever) wires to conduct the heat away wouldn't be much extra work.

Because the thermal mass is so small, it will hit equal temperature to source very rapidly then will actually impact heat transfer.

That's why copper heatpipes actually have a liquid within them as a heat transfer medium because the copper facilitates a better heat transfer strata but not over a distance.

Edit: And the copper cooling pins you're describing and showing are for the heat to be extracted from something actively travelling over it like air, water or in contact with the ground to increase the potential thermal mass.