Intel Sapphire Rapids utillises tiled, modular SoC architecture
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New Scalable Xeon moves from monolithic to multi-tile, adds multiple accelerators.
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Re: Intel Sapphire Rapids utillises tiled, modular SoC architecture
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Have these arrived in the nick of time to prevent AMD eating Intel's lunch?
If it was against Milan, maybe. But these are pushed back to H1 2022 meaning they'll be competing with Genoa.
That and the purported ~1500mm^2 total die area is nuts for such a low amount of cores.
Re: Intel Sapphire Rapids utillises tiled, modular SoC architecture
Hmm... maybe I'm missing something but isn't this just doing the same as AMD does with epyc.... the reason I say this is because according to Intel they just 'glued together' some desktop dies.... lol
Re: Intel Sapphire Rapids utillises tiled, modular SoC architecture
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Originally Posted by
LSG501
Hmm... maybe I'm missing something but isn't this just doing the same as AMD does with epyc.... the reason I say this is because according to Intel they just 'glued together' some desktop dies.... lol
Got the glue dig in there before me...
Re: Intel Sapphire Rapids utillises tiled, modular SoC architecture
Better not be Super Glue then , every time I've tried it , it came unstuck.lol.
Re: Intel Sapphire Rapids utillises tiled, modular SoC architecture
when will consumers see this technology in cpu's ?
Re: Intel Sapphire Rapids utillises tiled, modular SoC architecture
Well the HBM cache could be very interesting, though unless they have an IO die I guess they would need one stack per CPU die.
All the images are just renders though, we can't really tell what they are doing yet
