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Thread: IDF August 2005 :: Intel ditch HT technology

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    IDF August 2005 :: Intel ditch HT technology

    Intel have just stated that HT is not going to feature in their next architecture. This is a bit of a shock since they spent months messaging us that HT would be the most important move in microprocessor development, Intel have removed it (read - not included it) in their next generation processor.
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    I'm something of a simpleton on this subject, and I have little doubt the more expert of you will correct me if I'm wrong on this, but I think Intel's abandoning of HT is due to efficiency of transistor count when considering future designs using 4 or more real cores. I'm not sure of the transistor count impact that HT has on current CPU's, but I suspect that perhaps the cost of 4 cores with HT on all 4 cores may take the die space of what could have been a 6 real core CPU (this all theoretical on my part as I have no clue, once again, of the cost per core to implement HT in transistors).

    I have to say that was all TOTAL suposition on my part as I'm missing alot of important pieces of the puzzle on this, but I do think efficiency in multi core somehow has to figure into this descision to drop HT by Intel. There's no question a dual core CPU without any form of HT smacks a single core, HT enabled CPU all over the place in every benchmark I've seen published on the net except in the RAREST of cases. If this trend carries forward into multicore versus multicore with HT, new designs may benifit from not wasting space on HT functions that could be used for more cores instead when factored out over 4 or more cores. The only reason a P4 D EE has dual core AND HT is that Intel already has the HT transistors in place and might as well use them, and disable them on the regular Pentium D to differentiate the products only.

    In a dual core design that is intended to end there, this is just good business since thier not planning on sticking to netburst as thier core design anyway. But with a new core, or even a redesigned one for multicore use, triming up the individual cores of all detrius like HT units and who knows what else they could get away with streamlining out, would be one of thier concerns I would think.

    Just my 2 cents, that may be all it's worth

    Edit: If it's really as bada$$ as I expect it to be (here's hoping), I may FINALLY decide to buy a Intel product. I respected them alot in the P3 versus K7 days, here's hoping to see another one of those old time neck and neck battles that had us all on the edges of our seats. There's no question that the P6 cores have always rocked and it's newest revival in multicore, 64 bit, and on the P4's FSB will be a sweet setup and will be good for Intel.
    Last edited by moshpit; 23-08-2005 at 10:36 PM. Reason: just a last thought...

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    http://www.theinquirer.net/?article=25643

    Some more info from IDF 05 - Intel looks to be seriously concentrating on power issues this time around. The new chips allow cache to shared between cores when needed, and also allow for cache voltage to be lowered. Unused cores can also be powered off by the OS.

    Sounds like Intel chips are getting cooler - quite literally.
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    I think they are doing this for marketing reasons.

    My understanding is that the extra transitor count needed to add HT to a core is minimal, so once they have got HT debuged and working, there is no good technical reason to leave it out.

    However, on most desktop benchmarks it makes little difference, and often degrades performace, so there is little point in having it in a $499 dell for J.Random Luser.

    Instead, Intel will be keeping HT as a preemium feture for use in servers, and high end desktops, where it can make a significant difference, for use by costomers who know to configure their systems correctly.

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    Quote Originally Posted by iMc
    The new chips allow cache to shared between cores when needed
    wasn't hyperthreading disabled on recent BSD-based oses due to this horrendous potential security hole?

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    Quote Originally Posted by directhex
    wasn't hyperthreading disabled on recent BSD-based oses due to this horrendous potential security hole?
    No, someone pointed out on the Linux kernel mailing list, that there is a small, but theoreticaly possible security issue if a trusted and untrusted process are running concurently on a hyperthreaded CPU.

    It was shown, that the untrusted process would be able to get clues about what the trusted process was doing, by comparing the cache latency of different memory accesses, as clearly if the trusted process had allready put some data in the CPU's cache, then the untrusted process would get it much faster. This could be used to leak confidental data in a shared hosting environment for example.

    Clearly the same issue would apply to dual core CPUs where both cores share the same L2 Cache, such as current Athlon X2 designs.

    Having said all that, this is all theoretical, and as far as I am aware, no one has produced any exploit code to demonstrate the issue.

    There was talk a few months back about adding hooks to Linux, to allow security sensitive processes such as password or login, to request that no untrusted processes be scheduled on the same CPU while they run, but as far as I am aware, this has not been implemented.

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    Post More details on HT security issues

    Hi, I have found some links with details of the possible HT security issues.

    Here is the original paper that kicked it all of:
    http://www.daemonology.net/papers/htt.pdf
    (It is long and technical BTW)

    Kernel trap then reported the issue for Linux and FreeBSD

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    Quote Originally Posted by chrestomanci
    Clearly the same issue would apply to dual core CPUs where both cores share the same L2 Cache, such as current Athlon X2 designs.
    And clearly your unfamiliar with the X2's design of having independant cache for the cores. Both cores have thier own L1 and L2, no need for sharing. They do perform cache coherancy(sp?) checks similar to SMP systems, but that's it. The ONLY things shared in the X2 are the memory controller and the HTT bus, that's it, nothing else unless you count the packaging that both cores sit in being shared too

    Edited because I stated Intels even have seperate caches and the more I thought about the more I realized that I cared so little for Intel CPU's that I actually didn't know for sure on that point.
    Last edited by moshpit; 30-08-2005 at 02:05 AM.

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    I apologize for the double post, but truthfully I don't believe HT is being removed out of security concerns, or even JUST marketing, altho I think marketing has SOME bearing on it (which is why it would be kept on Servers, to bump the cost of them up with useless "features"), but I honestly believe (and here goes what LITTLE credibility I have left ) that HT is being cut as much for economy of design as for marketing. Since there's NOTHING HT does as well as dual core can, then it becomes a waste of space in a dual core CPU that costs power and heat that Intel's busily trying to cut. I expect HT to dissapear all together in the next 3 years as SMT becomes passe and multi-core level SMP becomes the standard.

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    moshpit, i think its because intel have realised they need to start selling it on Power Per Whatt.

    They've been making XScales for a while now, and noticed that AMD's heat output was more than the P4 with its hyperthreading had. But hyperthreading is somewhat of a waste of space (all be it a cunning waste of space) as the P-M shows good branching, a strong focus on branched pipelining is a better way to use idle bits of silicon.

    for everything but games, 3.0ghz is enough. even vista runs fine on a 800mhz (if you give it a good DX9 gfx card). As such they are realsiing that bill gates computer on every desk is now more a case of a computer in every toothbrush. As such power consuption is important. Good, if more joe-users use lower whattage, there will be smaller more silent boxes.
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    HT technoology cost very little more to priduce than standard processor tech.

    So i think we will be seeing HT released as a 'high end' solution

    this would mostly be a marketing scam as as far as i cna tell HT makes very little real world difference to performance.

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    Quote Originally Posted by MiNiMaL_FuSS
    HT technoology cost very little more to priduce than standard processor tech.

    So i think we will be seeing HT released as a 'high end' solution

    this would mostly be a marketing scam as as far as i cna tell HT makes very little real world difference to performance.
    When an application bombs, HT is very useful.
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    Quote Originally Posted by MiNiMaL_FuSS
    HT technoology cost very little more to priduce than standard processor tech.

    So i think we will be seeing HT released as a 'high end' solution

    this would mostly be a marketing scam as as far as i cna tell HT makes very little real world difference to performance.
    In desktop applications, then yes, On servers though it can make a huge difference. It is not for marketing reasons that IBM Power and Sparc servers support Hyperthereading. If somone is looking to spend $100K on a server, they they will do their homework, and if a feature like HT makes a genuine difference, then they will buy it, but not otherwise.

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