IBM and AMD's stressed silicon yields transistor performance boost
The 90nm chip manufacturing process is pretty well settled in now. Of course, many still remember Intel's Prescott, which wasn't just a simple die shrink, and so got a little... hot, shall we say? AMD took a different approach, shrinking first, adding features later, which perhaps proved the wiser option. Now, it's all about 65nm and beyond. AMD and IBM have been working on a 65nm process, which will go into mass production next year. Their latest techniques have yielded a 40% transistor performance increase.
Quote:
As with previous implementations of the technique, AMD and IBM's 'stressed silicon' process uses Silicon-Germanium (SiGe) to stretch a layer of pure silicon. The SiGe atoms are further apart than the silicon's, which stretch to align themselves with the SiGe lattice. The SiGe layer is applied to the insulating material used as the basis of the two firms' silicon-on-insulator process. Once the silicon lattice has been stretched, the SiGe layer is removed. The interaction of the insulator and the silicon helps retain the wider atomic spacing, a techique the companies call Stress Memorisation Technology.
[The Register]
