Intel's multi-FSB chipsets go back to the future
Intel's giving businesses chipsets with more than one front side bus to alleviate the clogged FSB in SMP systems, but isn't it a bit late for that?
Quote:
Past experiences make this current Intel approach very familiar - are they unconsciously following something that someone else already did in the last century? Well, let's look again at the Alphas, age 1998, 20th Century. That year, a new Alpha processor, 21264 (EV6), was announced, which, besides a new, exceptionally fast 4-issue out of order engine, also featured a new bus structure - instead of the shared 128-bit bus like on the 21164, now each CPU had its own 64-bit DDR point-to-point path to the chipset north bridge portion - that point-to-point path is also know as EV6 bus, used as you can guess in all the Athlon CPUs until Athlon64 came about. So, in the first 21264 generation, we had two chipsets, Tsunami (1998) and Typhoon (1999). Now, look at the diagrams and compare them with Blackford (2006) and Caneland (2007) - interesting?
[The Inquirer]
