would AMD be able to compete better with Intel if they doubled the front side bus for the higher end and dual core chips?
would AMD be able to compete better with Intel if they doubled the front side bus for the higher end and dual core chips?
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FSB has little to do with performance between different cpu types... you can't compare 200fsb axp with 200fsb a64 cpus... plus increasing default FSB = less overclocking room
AMD doesnt have an true FSB tho. That really went when they went AMD64.
TiG
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As far as 'front side bus' is really concerned, TiG is correct - AMD dropped this for a serial bus instead (hypertransport) which is faster than even Intels 4xFSB.
As far as the CPU clock is concerned (ie, the base rate to which a multiplier is applied) you've got a valid point, but bear in mind Intel have only just managed 266 with the upper model Core 2 Duos (the E6 series), though having done that they're now heading to 333 quite quickly. Raising CPU clock doesn't automatically mean more speed though - you're just as likely to have to drop the multiplier to gain stability. Instead AMD are concentrating on performing more instructions per clock, similar to the core 2 duo.
I think a better question is "why are Intel still bothering with an antiquated front side bus". They claim socket & memory stability, but then they mess with the socket every 6 months.
AMD will compete better when they can issue twice as many SSE instructions per clock than they currently can (next silicon will do that). They then need to manage the same sort of clock speeds that Intel are getting when overclocked, and that is the part where we will just have to wait and see!
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Intel have been using S775 for the last 3 years, the only thing that's needed to be changed is the electrical characteristics of motherboards for new processor compatibility. The main problem Intel has is that memory bandwidth hogs the FSB, DDR2 memory has stretched that design (apparent from bandwidth benchies), so either they increase FSB rates or add an independent bus to deal with memory i/o between the NB and CPU (I believe this is optimal) to retain modularity, or adapt AMD's design (which looks likely in the future from what I've read) which I personally think isn't such a great idea, I know it's better for latency to have the memory controller on the CPU die, but not so much for modularity and energy/heat conservation.
But like you say, we'll have to wait and see where it goes
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