So this has been bugging me...

[Terbinator]

What does the P55's use to connect/transfer to RAM - its own type of QPI between the IMC and RAM or something else. Just curious that's all as I cant seem to find a definitive answer anywhere on the web.

[Pob255]

Umm AFAIUnderstand nothing, on a p55 chipset motherboard the cpu is directly linked to the memory and the pci-e graphics slots by a QPI path in the PCB.

So to load data from the hard drive into the memory, the cpu sends the command to the chipset (via a QPI) to access the data from the hard drive, the data it then shunted by the on die memory controller into the memory via the memory pathway QPI

[kalniel]

What does the P55's use to connect/transfer to RAM - its own type of QPI between the IMC and RAM or something else. Just curious that's all as I cant seem to find a definitive answer anywhere on the web.

Wires! (Well, etched lanes in the motherboard PCB between the sockets to be more accurate).

There's no transfer protocol (ie QPI or DMI) between the memory sockets and the CPU socket because it's controlled on die at the CPU. There's no defined protocol between the IMC and the rest of the CPU die either (well, apart from 'dual channel DDR3')



If you need to define a protocol then it's dual channel DDR3. But really, it's better to think of the memory as literally being plugged into the CPU and it's just physically extended away with 'wires' for space reasons.

Umm AFAIUnderstand nothing, on a p55 chipset motherboard the cpu is directly linked to the memory and the pci-e graphics slots by a QPI path in the PCB.

So to load data from the hard drive into the memory, the cpu sends the command to the chipset (via a QPI) to access the data from the hard drive, the data it then shunted by the on die memory controller into the memory via the memory pathway QPI

Nope - no QPI at all on p55. QPI is a serial transfer protocol, like hypertransport. It would need logic at the receiving end to work with it, but RAM doesn't contain it, nor does the rest of the chipset in the p55s case. As your diagram shows, the CPU talks to the southbridge over DMI, not QPI.

[Terbinator]

While i appreciate your attempt Pob i already knew that (). Kalniel sort of answered my question which i guess really didn't have an answer.

Cheers anyway guys.

[Pob255]

I should of known form the diagram I posted

What I was saying was basically right, the memory and pci-e are directly connected to the cpu, I just got what a QPI is wrong