whys L2/3 cache so expensive??

[Swafe]

Always wondered, anyone know ?

I mean, ok its fast, buts it ridiculous, for example


3Ghz Celeron 256K cache? - 60 squid?

3Ghz P4 EE 2048k cache - 600? at least some are like a grand or something crazy


i cant remember if cellys and p4s are identical apart from cache or not, but even if they arnt 3 gig prescots are about 100ish, just over, and they have 512k - so since when was 1.5mb worth 900 quid?


its insane, itaniums have upto 9mb? cache, and there even more, like 5 or so grand a chip, 5 grand for 9mb ????


its fast....i know that, im sure its a load faster, than the fastest DDR, but still 5 grand for 9mb? ridiculous

[daverobev]

Because it takes up so much die. The pentium-m is more than half cache at 2Mb

And, because celly chips are chips with broken cache - thats how it works, cache doesn't work so it gets disabled, and you have a budget chip. Same speed in MHz, but 10+% loss in performance.

The only other differences with cellys are, I believe, 1: hyperthreading is disabled and 2: FSB speed is lower.

[Swafe]

look at flash memory, reduced sized MMC cards are TINY - they go upto a gigabyte too, the technology is there, honestly, is 2mb takes up half the die space, in this day and do you think that on a die we can only fit 4mb on it ? i think theres more to it

[shiato storm]

Because it takes up so much die. The pentium-m is more than half cache at 2Mb

And, because celly chips are chips with broken cache - thats how it works, cache doesn't work so it gets disabled, and you have a budget chip. Same speed in MHz, but 10+% loss in performance.

The only other differences with cellys are, I believe, 1: hyperthreading is disabled and 2: FSB speed is lower.

assuming this is true then surely there's a way to re-enable it and eek out a bit more speed before it becomes massively unstable...

[Swafe]

i imagine there might be, but noones yet to figure it out - i remember it working fine with the applebred durons, from 64?kb -> 256kb turning them from durons to amd XPs

[Rave]

You can't re-enable the cache on Intel processors, just as you can't adjust the multiplier. It's locked.

As for the cost of it, it does come down to die size as a previous poster has said. The Static RAM (SRAM) used for cache memory requires something like six transistors per bit of memory stored and has to run at processor speed (like 3GHz plus) whereas DRAM requires two transistors ber bit and runs at 200-400MHz. Bit of a cost difference there.

[StormPC]

It's partly the cost, but also the limited market and improved performance. One of the main things that make the newest CPUs faster than previous ones is the amount of cache and the way it is utilized. Cache makes a huge difference in performance in many applications. It costs money to stay at the top. You guys know new tech always costs an arm and a leg.

[Swafe]

well what about itaniums? there stupidly exspensive.....surew the chips are a fair bit, but when u add more and more cache the prices skyrocket into the thousands

and some only run about 900mhz or a ghz ? couldnt they recycle cache of old P3s cache cos they run the same speed? in cache terms 1ghz sounds slow, if the latest p4, 3.6ghz the cache needs to run at 3.6ghz, and this needs to run at 1ghz isnt it old tech??

[daverobev]

The cache IS the CPU...its all in one when fabricated, the whole CPU is made from silicon wafers...very very expensive and costly and whatnot. P3s were constructed using larger transistor sizes (you know when they say .18 micron? .15? Now going to .09? Thats 90nm, 1 times 10 to the power minus 9 (please correct if thats wrong, been a long time since I was in school/at uni...)). P3s were...25 micron, some of them, I think, moving to 18 for coppermine??? Er not that its relevant!

Its a case of horses for courses. Probably, server chips would be crap for gaming just like a ferrari is useless for transporting a bed. Different design, different strengths and weaknesses. x86 is a flawed platform (ie lots of compromises, delays in the architecture, I believe), but retains compatibility and scales well...these server chips don't need to be compatible, they need to...do whatever they were designed to do.

Don't quite know how to explain better than horses for courses!

[smtkr]

Ha, remember those slot one packages with off-die L2 cache? It did make it cheaper to put more L2 cache in the cartridge, but they had to run it at half speed.

[Steve]

Ha, remember those slot one packages with off-die L2 cache? It did make it cheaper to put more L2 cache in the cartridge, but they had to run it at half speed.

L2 cache used to be on the motherboard before that, IIRC.