How Quad-pumped bus works ??

As teh title, i always wonder how Intel quad-pumped bus work. I understand that DDR transfer 2 bits per cycle using the up and down of the signal curve, but 4 bits ?? How they do that :D

Well, its more, Intel doing nothing new, just naming something differently..

I BELIEVE, that its just DDR and Dual Channel, and Intel's marketing have gone and said, "Two duals equals a quad!!"

It's not DDR+Dual channel. A quad-pumped bus can be transfer data 4 times per clock per channel. AGP 4x is another example of a quad-pumped bus.

The specifics seem unclear, but I'd assume rather than using rising and falling edges, they just multiply up the clock frequency at the bus interface.

Intel CPUs are "quad pumped", meaning they send 4 instructions per clock cycle. This means that if you see an FSB of 800MHz, the underlying FSB speed is really only 200MHz, but it is sending 4 instructions per clock cycle so it achieves an effective speed of 800MHz.

this is...

qdr ram has unlike DDr ram 2 bi-directional read / write ports effectively
doubleing the transfer rate.

also mean's more wires between the ram and the controller.

But mean's for every read it can write at the same time were I believe DDR its a either
or setup.

It achieves 4 data transfers per clock by using two clocks which are 90 degrees out of phase. Data is transferred on the rising and falling edges of each clock. This is called quadrature clocking. In fact IIRC there are 4 clocks - each clock is a differential pair so there is the clock and its complementary clock.