HBM2 memory wafer shown off by SK Hynix

[HEXUS]

This memory will probably debut on Nvidia Pascal GPU graphics cards next year.

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[Nobull]

Jesus AMD might really pay for its tardiness in bringing the 300 series to market. If they only have 6 months on Nvidia before they release cards with double the memory bandwidth, doesn't really bode well for AMD.

[shaithis]

Jesus AMD might really pay for its tardiness in bringing the 300 series to market. If they only have 6 months on Nvidia before they release cards with double the memory bandwidth, doesn't really bode well for AMD.

I have a feeling only 4k+ resolutions are really going to see the benefit of the extra bandwidth anyway. I doubt this is going to sway the market one way or the other yet.

[chrisFletcher]

Jesus AMD might really pay for its tardiness in bringing the 300 series to market. If they only have 6 months on Nvidia before they release cards with double the memory bandwidth, doesn't really bode well for AMD.

You're right, but I don't see how AMD could do anything else, delaying the 300 series to put the newer memory on just makes it worse

[DDY]

Why is the HBM chip "1GB" where the DDR is "4Gb"?

[scaryjim]

Jesus AMD might really pay for its tardiness in bringing the 300 series to market. If they only have 6 months on Nvidia before they release cards with double the memory bandwidth, doesn't really bode well for AMD.

Depends what they're targeting with it. For gaming, I can't see them needing that much bandwidth: R9 300 is going to have almost twice the bandwidth currently available to Titan X; if Pascal goes for a 4-stack HBM2 arrangement it'd have 4x as much. I don't think gaming graphics are bandwidth limited at the moment: the R9 285 was a great example of getting better performance from less bandwidth by using intelligent texture compression and other tricks. So while the headline bandwidth figure would undoubtedly look impressive, it would largely be wasted for gaming. And while I'd be tempted to suggest it's aimed at compute, nvidia haven't exactly been letting their recent chips stretch their compute legs. Perhaps the reason GM200 is so compute limited is because NV know they need better bandwidth - only time will tell on that one.

Another reason to wait for HBM2 could be the increased density: a 2-stack HBM2 arrangement would give similar framebuffer and bandwidth to AMD's 4-stack HBM1 set-up, but with less complexity/traces/controllers. That saved die space could go into more shaders/cache/etc.

There's a lot of conjecture involved, but I honestly don't believe that nvidia are going to come up, within the next year, with a GPU that needs > 1TB/s memory bandwidth...

EDIT for crosspost:

Why is the HBM chip "1GB" where the DDR is "4Gb"?

Erm ... because it is? Single memory dies tend to have their capacity quoted in gigabits. HBM is a stack of 4 2Gb dies, making a cube with 8Gb capacity. I assume they use 1GB to differentiate between a stack and a single die....

[Ttaskmaster]

Why is the HBM chip "1GB" where the DDR is "4Gb"?

It's "twice as fast and twice as dense", so you don't need as much, I'm guessing...
HBM1 and HBM2 are both smaller too, so you can fit more of them on a GPU, resulting in cards with "32GB of RAM" - Kiss your srubbishrubbishrubbishrubbishy new Titan X goodbye... or sell it to me for cheap!

[DanceswithUnix]

Jesus AMD might really pay for its tardiness in bringing the 300 series to market. If they only have 6 months on Nvidia before they release cards with double the memory bandwidth, doesn't really bode well for AMD.

You mean Nvidia might benefit from being so tardy that they might as well use HBM2?

I wonder if this technology will ever be relevant to the under £150 market that I tend to swim in.

[shaithis]

I wonder if this technology will ever be relevant to the under £150 market that I tend to swim in.

Of course it will, I would bet that as soon as yields get high enough we will see stacked RAM becoming the norm and those horrid budget cards we see with GDDR3 coming with GDDR5 instead.

[DanceswithUnix]

Of course it will, I would bet that as soon as yields get high enough we will see stacked RAM becoming the norm and those horrid budget cards we see with GDDR3 coming with GDDR5 instead.

Anyone else remember the Pentium Pro? It had on package cache to try and make it keep up with the risc chips of the time. It was made quite clear that the technology was stopgap and would never go mainstream.

For really budget devices I can imagine attaching a ram die or two on top of the gpu die, but if an interposer is required then costs go up and I wonder if there would be a better way of spending that money to make a card faster.

[stevie lee]

Jesus AMD might really pay for its tardiness in bringing the 300 series to market. If they only have 6 months on Nvidia before they release cards with double the memory bandwidth, doesn't really bode well for AMD.

or to look at it another way.

AMD will have 6 months+ with actual market feedback on how well they've managed to use this new memory and integrate it. so their second generation will be a lot better than what will be nvidias first generation with the memory.

any problems with cooling, interfaces drivers and such will hopefully have been ironed out in AMDs card by then.
so from my point of view, nvidia will be playing catch-up even though their launching with faster stuff.

[scaryjim]

...I wonder if this technology will ever be relevant to the under £150 market that I tend to swim in.

If AMD do find a way to connect two stacks to a single 1024-bit channel, they'll be able to run 2GB cards on a single HBM 1 channel, with ~ 160GB/s bandwidth, equivalent to a 256bit 5gbps GDDR5 interface: i.e. the one already available on sub-£150 cards. Unless the HBM controller is significantly more complex to implement than the GDDR5 one, I can't see any reason they'd not trickle the technology down to the midrange.

[scaryjim]

...AMD will have 6 months+ with actual market feedback on how well they've managed to use this new memory ...

AMD have a bit of recent form when it comes to new technologies - they went GDDR5 early, they went 40nm early, and both of those turned out pretty well. OTOH, nvidia learnt a lot from AMD when it introduced kepler & tuned the performance per watt characteristics of the architecture - to the extent that they're now comfortably ahead on that metric (for gaming, at least). SO it could go both ways: AMD could do well with a first foray into the technology, but equally nvidia could learn from AMD's experience to smooth their own transition to HBM. At the minute, it's anyone's guess as to how it will all shake down...

[canopus72]

What worries me about nvidiot moving to HBM2 is that Jen Hsun Huang being the slimy little snake that he is, may well find a way to create a legal loop hole that will cut AMD out of using HBM2 which is 3D and not 2.5D stacked HBM (even though AMD with it's 'partner' Hynix teamed together to invent HBM in the first place). AMD better keep a close eye on SK-Hynix over the next 12 months or so.

[whatif]

Jesus AMD might really pay for its tardiness in bringing the 300 series to market. If they only have 6 months on Nvidia before they release cards with double the memory bandwidth, doesn't really bode well for AMD.

Given AMD will have six months to play with version 1 (v1) before they can access version 2 (v2), plus have the benefit of the newer tech when it comes out, I don't see what the down side is.
It does not say the Nvidia will have absolute rights only to the v2, just that they are going to wait until then to release their new card. Given the potential they had with the 290's but the problem they faced with energy use and heat, it would seem prudent to wait and use better tech when it is available - meaning grabbing v1 and implementing it to minimize the old problems. Then grab v2 as an upgrade.
That would seem sensible to me anyway. I am sure others will disagree.

[devBunny]

Why is the HBM chip "1GB" where the DDR is "4Gb"?

Single memory dies tend to have their capacity quoted in gigabits. HBM is a stack of 4 2Gb dies, making a cube with 8Gb capacity. I assume they use 1GB to differentiate between a stack and a single die....

Not just the stacking but also the data access. A bit like a ram module on a chip; a RoC for your SoC.

Wikipedia: HBM uses more I/O pins per memory package, up to 1024 (DDR3 and GDDR5 used 8-32 I/O pins per memory chip).[5] Memory package in prototypes of HBM consists of 4 memory dies, each implementing two independent 128-bit channels (193 I/O pins); total 8 channels per package.

http://en.wikipedia.org/wiki/High_Bandwidth_Memory