Samsung looking to define post-DDR4 memory

[HEXUS]

Prototypes of next-gen memory should appear in 2018. Adoption to follow in 2020.

Read more.

[J3FFW1SH]

I was under the impression that HBM was the answer to inefficient RAM, what did I miss!

[edzieba]

I was under the impression that HBM was the answer to inefficient RAM, what did I miss!

HBM does you no good without the interposer. And because the interposer needs to be fabbed on a semiconductor process (rather than a PCB) that gives hard limits on physical size, and thus maximum capacity. HBM also gives a very wide IO, but not a particularly high clock rate (which is how it achieves power saving). Great for moving big chunks of data in and out of on-die cache, but not so good for low-latency access to small bits of data.

[blotto5]

I was under the impression that HBM was the answer to inefficient RAM, what did I miss!

HBM is video memory, which requires a very high bandwidth to move large chunks of data. CPU RAM requires low latency for smaller chunks of data more often.

[kalniel]

Well will you just look at that shrinking desktop market

[DanceswithUnix]

Well will you just look at that shrinking desktop market

Most people want laptops, even if a desktop is what they need.

Phones get replaced very fast still, probably 2 years if you don't drop it. With the number that get broken, the average replacement is probably well under 2 years still. I think that inflates the mobile market quite heavily.

I suspect that is about to change though. New phones are getting pretty good even at the low end and people around me seem to be increasingly on SIM only contracts and can replace their phone on whim or need. As the technology settles down I can see 3 years being the new norm for phone replacement before long.

[DanceswithUnix]

HBM does you no good without the interposer. And because the interposer needs to be fabbed on a semiconductor process (rather than a PCB) that gives hard limits on physical size, and thus maximum capacity. HBM also gives a very wide IO, but not a particularly high clock rate (which is how it achieves power saving). Great for moving big chunks of data in and out of on-die cache, but not so good for low-latency access to small bits of data.

HBM is a 3D technology. You might only be able to have a few stacks of RAM, but those stacks can be quite high, so a CPU with 32GB of ram on it is quite possible some time next year.

I don't think latency is actually that bad. RAM doesn't transfer just a word of data and hasn't for some time, it transfers a burst of data to fill a cache line in the CPU. If the bursts are shorter because the interface is wider, then the CPU may have a shorter wait for the last burst to finish before it can start the next access. Also, if you know the properties of the main ram are high bandwidth then you can probably tune the cache prefetchers to make use of that.

TLDR: Modern ram is complicated, I'm sure people at Intel and AMD will be making it workable.