Read more.And Apple sends out invites to its WWDC 2018 keynote: Mon 4th - Fri 8th June in San Jose.
Read more.And Apple sends out invites to its WWDC 2018 keynote: Mon 4th - Fri 8th June in San Jose.
Whelp, ill give them credit for this move. 7nm is a big deal, and obviously apples knows it, and will beat everyone else by having first ever. Nice move apple
Any chance this will affect (read: delay) CPU/GPUs for PC thanks to fabs catering to the big guys first?
I thought most of the sort of 7nm CPU/GPUs we'd be buying were slated for 2019 releases, i guess if they hit their predicted production volumes the 7'ish month delay should mean demand from the likes of Apple would be dropping of around that time.
I think that is the plan, aim well down the production ramp up timeframe. These days desktop stuff just isn't profitable enough to get first dibs on anything. Mind you, it could be argued that this 7nm will be equivalent to Intel's 10nm which technically they are shipping product on even if it is only trickling out with apparent difficulty. If TSMC can do actual production volume, then they may have overtaken Intel for now.
Mobile has been king of new nodes for a while now, selling very small and very expensive chips (where power consumption has to be kept under tight wraps) works a lot better with cutting edge nodes than trying to set new records for the number of transistors in one chip
If apple hadn't outbid everyone else then someone else would have filled the gap - it's very unlikely that the difference in price for the first few wafers was enough to crash them into production any sooner. This isn't a new standard that apple are pushing, like USB-C only on laptops, it's just a gradual improvement of the previous stuff (and that every other chip company would love to use)
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Not really, GPU and most enterprise CPU dies are far too big to get economic yields from a new node shrink. Desktop CPUs are also affected by poor yields but to a lesser degree thanks to their smaller dies. Nice tiny SoC dies make for a great pioneering mass production product because their small die size means defects are less likely to negatively affect the dies, more working dies means cheaper dies and more profit. SoCs and other small dies will hammer out the production process for the new node that will be make using it for CPUs, then GPUs more viable. It's also why AMD has gone in the direction of breaking up the dies into core complexes that are assembled on package and getting in on 10nm mass production before Intel, and others are following suit.
i3's are small chips, by desktop standards. Ryzen is more than twice that for RR and SR (I'm pretty sure I recall reading somewhere that the new APUs are the same size as the CPUs), and any new GPU that can afford a new node (1180, whatever comes after vega) will be many times larger. Intel's 10nm dual core is an exception for non-phone parts
And the A11 was produced with the more mature 10nm FinFET process. Intel is also sorta shipping some laptop i3 chips on 10nm. Apple will probably opt for a smaller die for 7nm. Then again they have the suckers/margins for gambling with a 'big' 7nm chip if they want to cram more transistors in there.
OK, I said i3 as Intel try and hide their die sizes these days and I was too lazy to dig around and do maths.
i5 8250u is 122mm^2 on a 14nm process: https://en.wikichip.org/wiki/intel/core_i5/i5-8250u
Assuming Intel are right that their process is better so their 14nm is equivalent to someone else's 10nm, then that means that is close enough comparable with the A11 on feature size. So the A11 is 72% of the size of an i5.
I'm far from an Apple fanboy, I don't own *any* of their kit, just running the numbers those are pretty big for a phone.
I tried to find the die size for a raspberry pi, but got bored Note the cost of getting masks done at these feature sizes it well out of hand, I really don't see that it makes sense on a small chip to bother when you could just make a bigger 28nm chip for peanuts and get it made pretty much anywhere. You have to really care about having a lot of kick in a small space.
It's difficult to compare different processes even from the same foundry let alone different companies, you could probably try but you'd need to know transistor count per mm^2 as without that you're basically guessing at the density and how tightly packed everything is.
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