Read more.But the new chip appears to confuse SiSoft Sandra's detecting mechanisms.
Read more.But the new chip appears to confuse SiSoft Sandra's detecting mechanisms.
do I need a new workstation? yes, mine if 8 years old. do want one of these, yes, but I wish it had DDR5. uggghhh, have to wait another year...
Replied without reading the article?
Alder Lake is meant to be DDR5 by all account as mentioned in the article and the Wikipedia
https://en.wikipedia.org/wiki/Alder_...icroprocessor)
Also somewhat doubt that a 8C+8C BIG.little type CPU is be best fit for a workstation.
Yeah I just don't get the 'logic' in this approach on a desktop, it's not like current cpu's are excessively power hungry when in low power states either.
I can understand the idea for laptops and tablets because they do need power efficiency but desktops are plugged in to a power supply lol.
Having said that I am curious about 'real performance' on desktop just to see how it stands up against AMD etc.
What are the extra 500 pins doing?
So it's 16/32 or 16/24 ?
Meh, if Intel's 10nm wafer starts really are "shockingly small" then we won't really be seeing any anyway.
At 1.4GHz it looks like these are intended for laptops, but then most Intel parts are. Why does the title say desktop?
DanceswithUnix (07-10-2020)
I wonder if this is for the corporate purchasers who are asked to buy an 8 core machine; ooh look that one is cheaper, box ticked. No good performance required.
It would make the die size a bit smaller so they get more die per wafer helping their supply issues, specially on the almost non existent 10nm lines.
Yeah that's fair. I wonder if the cache sizes are actually measured as well, or if it will be getting that wrong.
Addled. The Adler Lake design sounds confusing for users/developers.
I haven't seen Intel announce PCIE5 on anything other than Agilex FPGA, Sapphire Rapids Server chip and Ponte Vecchio GPU. Yet, now I've seen notebookcheck and this article mention PCIE5 on Alder Lake.
If Intel has implemented CXL on Alder Lake's PCIE5, does that open up the possibility of master/slave configurations for multiple low power CPUs that could be used as accelerators in a scalable way?
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