AMD demos Ryzen 9 5900X prototype with added 3D V-Cache

[HEXUS]

AMD / TSMC's 3D stacking shown to boost game performance by 15 per cent on average.

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[CAT-THE-FIFTH]

Both AMD and Intel have talked about the use of such stacking,but the bigger issue is going to be cooling each layer sufficiently. Is the extra cache on top of the existing cache locations on the chiplet?? It would make sense of the copper connection layer to be over the cores??

[kalniel]

Both AMD and Intel have talked about the use of such stacking,but the bigger issue is going to be cooling each layer sufficiently. Is the extra cache on top of the existing cache locations on the chiplet?? It would make sense of the copper connection layer to be over the cores??

That's what the picture seems to show - the CCDs remain single layer and covered only by a structural substrate (that should conduct thermally), so as long as the caches themselves don't generate huge heat (and I don't think they do) then it should be fine.

[Kovoet]

Think I got my 5900 at the right time.

[mers]

Nice , I like to see somethging well stacked.

[Iota]

Both AMD and Intel have talked about the use of such stacking,but the bigger issue is going to be cooling each layer sufficiently. Is the extra cache on top of the existing cache locations on the chiplet?? It would make sense of the copper connection layer to be over the cores??

I guess it depends on where that copper connects to? Looking at the images it doesn't connect to anything aside from the lower layer, so I'm not sure how they intend to transfer heat away? Unless they somehow connect it to the IHS, I'm not sure how they intend to do this.

[habilain]

Both AMD and Intel have talked about the use of such stacking,but the bigger issue is going to be cooling each layer sufficiently. Is the extra cache on top of the existing cache locations on the chiplet?? It would make sense of the copper connection layer to be over the cores??

The cache die is going to have the same thermal conductivity as the CCD die, as they're made with the same materials. Hence it's a non-issue in terms of being an extra layer inbetween the CCD and the IHS - the rate of conducting heat away from the CCD is going to be basically the same (indeed, the extra copper might improve things, by distributing the heat over a larger volume). Therefore the only real difference is going to be the additional heat generated by the running the extra cache, but this is going to be a) fairly minimal and b) higher amounts of cache result in firing requests to memory less frequently, which means less power draw from that subsystem.

If this were stacking two or more CCDs, then thermals start to become a much bigger issue as each of the CCDs generates a lot of heat. But for cache? I doubt it'd register at all.

[LSG501]

I guess it depends on where that copper connects to? Looking at the images it doesn't connect to anything aside from the lower layer, so I'm not sure how they intend to transfer heat away? Unless they somehow connect it to the IHS, I'm not sure how they intend to do this.

There's a supposed leaked image (3D render) of what the heatsink etc is going to look like on zen4...it's a bit of a weird design and pretty unlikely in all honesty but the stepped in parts could be linked to how they intend to connect it all.

https://www.tomshardware.com/news/am...inating-design

[Iota]

it's a bit of a weird design and pretty unlikely in all honesty but the stepped in parts could be linked to how they intend to connect it all.

https://www.tomshardware.com/news/am...inating-design

Stepped in parts look like they could accommodate a slightly different heatsink design, so it draws from the side as well as the top.

[DanceswithUnix]

This technique if applied to GPUs could make for variants with and without a large infinity cache.

[PMMEASURES]

Not sure cooling an issue, the Silicon substrate probably in the region of thermal conductivity likely 120-150 Wm.k or better in its working range so the thermal TIM still be a bottle neck for wicking the heat out.

[Tabbykatze]

It looks like AMD confirmed Zen 3 refresh to Ian but it looks like it won't be an AM5, more like an XT thing.

Observably it looks like beta testing the technology on known stable systems to help tweak and fix for future releases.