The IO die is physically much smaller - Anandtech has some measurements.
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The IO die is physically much smaller - Anandtech has some measurements.
Yeah i expected the io dies to be different. with 14nm its cheap to do as well. I'm quite surprised how much smaller the am4 io die is but chucking 6 ddr4 channels off does help, along with the extra security stuff.
one good thing with chiplets is that doing 16c is easy but you don't need to worry about trying to do 12c, as you can use 2x chiplets (with 2 defective cores from each die) or you can use two of those chiplets in two seperate hex core chips.
chiplets are quite kind on defective dies.
more i think about chiplets, the more benefits i see to them, with very little downsides as long as they were small enough. Bulldozer era made that impossible - but at 7nm it becomes completely sane to do so
Pretty big though. 123mm^2 is about the size of a Coffee Lake quad core with integrated graphics.
Traditionally northbridge style designs are pad limited which is why they started putting integrated graphics on motherboards, to find something to do with the silicon area you get with that many I/O bumps around the outside. So I wonder what they do with the space? Huge cache perhaps, or some graphics, or both.
Aye, there are still plenty of questions over Zen2 - along with what you said, how many cores for a CCX?
But in terms of die size, that alone doesn't necessarily imply manufacturing cost when comparing two different types of IC e.g. I imagine it has far fewer layers and therefore lithography steps vs cores and will be running at a lower clock speed with less power distribution. It's fairly big vs CPU sizes but it's not unreasonable for a kinda-Northbridge IMO. And given they've seemingly hinted towards the possibility of 16C versions, the die presumably has the IF logic for another core chiplet to connect.
They're still being very quiet about details though!
Part of me is wondering if that I/O die will be used for Threadripper 3 - i.e. it's got 4 channels with only 2 in use for Ryzen 3 but it's got the ability to connect 4 chiplets and 4 memory channels. The size suggests otherwise and I imagine that instead AMD will use the Rome I/O die for Threadripper as I can't see Threadripper volumes justifying another die's development cost
Anyone want to place bets on the I/O die having some amount of memory (L4 cache) or not, even at 14nm does it seem bigger than what's needed just for I/O?
I think it needs enough prefetch buffering to compensate for the SerDes hops that IF uses to cross from cpu die to the I/O and back, so yes probably an L4.
It is also interesting to note that on the GF 14nm process weighing in at 123mm^2 with 8 PCIe lanes, two memory controllers and a bunch of high speed serial I/O for HDMI & displayport is the RX560. Now the 560 is more of a square chip to maximise the amount of logic on the die, whereas the I/O chip here is rectangular to expose more edge for I/O. So this chip has fewer logic transistors but more connectivity than a 560, but I'm half expecting the I/O controller to contain a GPU if it has my guesstimate of 2.5B transistors to use up.
That's ... a curious concept. Would there still be space if we assume the IO chip has room for up to 4 chiplets/4 memory channels (and, I guess, 64 PCIe lanes) (so it can be used for Threadripper as well as plain Ryzen)?
Let's see - a full Zeppelin die (on the samne 14nm process) is 192mm2 and 4.8Bn transisitors. According to https://en.wikichip.org/wiki/amd/mic...en#Scalability a CCX is 44mm2 and 1.4Bn transistors. Two of those is 88mm2 and 2.8Bn transistors, leaving Zeppelin's non-CCX budget (2 memory channels, 32 PCIe lanes, peripheral IO and various IF links) at 104mm2 and 2Bn transitors.
So, speculatively, the Ryzen 2 IO die may have ~ 19mm2 and 0.5Bn transistors to play with over a Zeppelin uncore. I dfon't see any way they can cram double the oncore resources in to that, and it doesn't sound like much space for a GPU either, it's barely enough for a bit of L4 cache (the L3 in Ryzen is 16mm2 per that source)...
As far as Threadripper goes, I did wonder if they might engineer the smaller IO die so you can link them together, and TR will end up being essentially the same as it is now - two Ryzens linked over IF - the only difference would be that you'd be linking two IO chips together rather than two full dies...
I'd gone through that very thought process myself! Likewise, I think it's too small for that though.
It seems a fairly outlandish thing so normally I'd doubt it, but so is a lot of what AMD is doing at the moment so it wouldn't surprise me.
Interesting analysis - add to that you need the on-package interface to connect to the chiplets and you might have used up that 19mm2. I don't think 123mm2 is all that big for what it is - uncore takes up a lot of space on modern CPUs, and don't forget that's one reason for doing this in the first place given its relatively poor scaling.
As I've mentioned - often - in conversations about Ryzen, even going off-CCX on the same silicon has a significant latency penalty. With chiplets, you're talking about the potential for half your L3 cache to be on a different piece of silicon completely. If the only way to access that is a multi-step process via the IO chip, you're going to have absolute killer latency once a thread exhausts its chiplet's cache. Having a mirror L4 cache in the IO chip would help reduce that. And AMD have to minimize those cache latencies if Zen 2 is going to perform well in the real world...
It's worth remembering that there must be silicon in a Zeppelin die that connects the CCXes to each other and the IO/memory controllers etc., and that would all be included in the uncore in my analysis. So that shouldn't really need any extra silicon space, unless the IO chips have a lot more IF connectivity than a Zeppelin...
FTFY, at least i think i have as IIRC each individual CCX is fabricated on a single piece of silicon.
That touches on something I've been thinking about, we know currently Zen shares its L3 cache between all cores and all CCX's so it seem unlikely that would've changed with Zen2, that got me thinking why you'd want or need and L4 cache in the I/O die, if we assume the CCX's are connected directly to each other and sharing their L3 caches (very probable) then what's the advantage of adding L4 to the I/O die?
This may sounds nuts but i thought I'd spitball it with you guys, wouldn't it make more sense to move the separate pieces of shared L3 cache within each CCX to the I/O die, you're not really increasing latencies as each cores L3 cache has to remain consistent with every other core, both within it's own CCX and others so there was already a latency penalty in doing that, moving the L3 into a separate block means you reduce, or completely eliminate, the need to directly connect each CCX to each other as you no longer need to keep the data consistent between CCX's, you only need to keep it consistent with the L3 cache on the separate (I/O) die.
That makes it seem like an L4 cache in the I/O die seem not only pointless but more complicated than needs be as you now have to keep two caches consistent, and on of those is divided up between CCX's, thought?
Also a side thought i had, with Zen2 having a separate I/O die and 1-2 CCX's could/would it make direct die cooling safer? I know IHS' became a thing because smaller dies increased the risk of chipping the die but with three separate dies on a single package isn't that risk reduced what with spreading the load, obviously it would be a right PITA as you'd have to separate a IHS that's been soldered on and you'd have to reduce the Z height of the heatsink but it would be interesting to see how effective direct die cooling would be.
No, no you haven't, and this is why I keep mentioning it.
Each zeppelin die has 2 CCXes. Each CCX has 8MiB of L3 cache. The CPU reports itself to the OS as an 8-core, 16 thread chip with 16MiB of L3 cache, but in reality it's 2 4-core, 8-thread, 8MiB L3 cache chips with a lot of clever, fast interconnects.
Here's the relevant graph from Anandtech's 2nd-gen Ryzen Deep Dive:
https://images.anandtech.com/doci/12...el%20Cache.png
See that big jump for Ryzen between 4MiB and 8MiB (n.b. that's a log scale graph, so the jump is actually even bigger than it appears there)? Notice how it happens at exactly the same point as the 8MiB Ryzen 2400G runs out of its 8MiB cache and hits main memory? Notice how @ 8MiB strides the 2700X has roughly the same latency to cache as the I7 8700k has to main memory?
That's the performance issue I talk about. It's nothing to do with going off-silicon, because the 2700X is one piece of silicon. It's all about the latency delay once a CCX fills its 8MiB of L3 cache and has to grab data from another CCX somewhere. That's slow on the same silicon. It's slower to another piece of silicon across a substrate (a la Threadripper), which would be the best case scenario in a multiple chiplet design*. If you had to travel across a substrate to an IO chip, from the IO chip to a second chiplet with the other CCXes on, then back to the original requesting core via the IO chip again, that's likely to be worse than going straight from the IO chip to the main memory.
As someone's said recently (either in this thread or elsewhere on Hexus) AMD have back-engineered from a fully integrated SoC to a packaged northbridge + base CPU. They've even decoupled the memory controller from the cores, so we're right back to - effectively - using FSB. It's basically a mash-up of the Core 2 quads and the early Core i3/i5 with IGPs. It needs amazingly good cache management and interconnects to hide the latency penalties.
* a little note on a chiplet design: if you want to keep cache accesses to other chiplets down to a single transfer across the substrate you'd need coherent links between all the chiplets That means each chiplet would need bumps and traces to 8 other chips (1 to the IO chip and 7 to the other chiplets), as well as logic and transport on the silicon itself to manage the access. That strikes me as a lot of extra silicon in each chiplet vs keeping a supplemental L4 cache on the IO chip and keeping the chiplets down to a single link to the IO chiplet.
Apologies, i keep mixing up my dies and CCX's don't i. :eek:
Not that it matters much but that Anandtech graph doesn't do a great job of showing what you're talking about IMO, i think PCPer did a better job when they looked at the 1600X and compared a 1800X with an Intel 5960X.
https://www.pcper.com/files/imagecac...0/ping-amd.png
And to be fair the ping times between cores within a CCX are lower than between cores on an Intel CPU, 80ns vs 40ns, it's only when traversing between CCX's that there's a jump up to 140ns.
I think I've got you at it now. ;) It would only need traces in the substrate for two/one die not 8 chips as like you say each die contains 8 cores so their connections are handled within the die.
I was among them (though by no means the only one). Intel have done good latency hiding in the past, and I wouldn't be surprised if AMD had picked up a lesson or two from their own console implementations too.
A possible benefit of northbridge is you get to really tune/push that memory controller, which might help counter a touch of latency as well.
I hadn't seen it mentioned here yet, but did you see what Anandtech said about the power?! They estimate it's nearly twice as energy efficient compared to a 9900K during Cinebench. That's got to be one of the gains by going with mixed die processes - you can keep each in the preferred power-frequency window without having to compromise quite so much.
It is next to main memory which needs to be coherent with the L3 cache, so coherency is a wash as the logic is pretty much there anyway.
Northbridge cache is I believe what made the Nvidia chipset motherboards so fast when they came out back in the Athlon era. Usually the L3 cache hides memory accesses of the memory controllers, but if they are on another piece of silicon then they should be tuned to hide the latency of the fabric to the IO controller, the controller can have it's own cache tuned to hide the memory latency also acting as a destination for any prefetchers it might have.
That makes sense, the logic already being there. What gave me pause for thought was more the extra complexity of the traces in the substrate, yes an L3 cache shared between chiplets and an L4 cache within the I/O die is a better solution from a performance perspective but it also means more traces within the substrate as each chiplet has to have two connections, one for connecting to all other chiplets and another for connecting to the I/O die.
I believe the estimate was 75W at performance equity. It's pretty insane, given what Intel do to their TDP definitions (iirc the 9900k actually pulls around 130W peak for the test). Of course part of that on n-thread tests is the comparative efficiency of AMD's SMT implementation, which I do wonder if they've tweaked further. But I'm sure that using different processes for the different structures has all sorts of benefits...
Of course if that 75W is accurate they've got another 30W to play with in the TDP stakes. A quick comparison of the 2600 and 2600X (65W v 95W) suggests that might give them as much as 10% additional performance.
Or, to look at it another way, it suggests that any non-X parts (which I'm assuming will come to market with a 65W TDP) will be almost as fast as Intel's fastest available parts.
Chapeau, AMD...
Ooooh, now there's interesting …. I'm sure I've read something while I've been looking at all this that says the Ryzen L3 cache - as a victim cache - can't be pre-fetched into? Adding an L4 cache to the IO die that could be prefetched into could really work for them....
EDIT:
No idea why this has only just occurred to me, but by moving to chiplets + IO die, they've totally removed the NUMA considerations from all their processors (well, assuming they make a separate IO die for TR4). Which means the higher core counts should play a lot better with Windows on desktop too....
EDIT 2:
In relation to which, does anyone else get the feeling that this was the real plan for Zen all along, and the monolithic die and MCMs were really just a stop gap while they got their ducks lined up?
I'm not sure. I think they'd have preferred to get MCMs working better. This is almost like saying we'll hide off-die latency for some threads by giving all threads the same extra latency by making it always off-die. There is still the core-core communication or shared cache lookup to be considered and that's going to take a hit between chiplets.
Chiplets make a lot of sense financially and the latency isnt such an issue in a lot of the HPC tasks (that I work on at least), especially when you consider with 64 cores I am going to be able to process much more stuff in parallel.
*shrug* I suppose it's going to be another wait and see moment. If they've done a good job it'll just be a great processor - if they've not then it'll be another generation where AMD are the go to for a particular set of workloads without being goods in all workloads.
What I'm finding really interesting is just how much all of this calls back to 5+ years ago and the talking about 2.5D stacking - only back then everyone seemed to assume we'd be using interposers, and here were are still wiring everything through the substrate.I can only assume that's basically because there's no significant performance advantage to interposers at this scale and they would introduce significant additional cost, but - just like jetpacks and martian colonies - I can't help feeling lied to... ;)
I think it's more to do with how much they've managed to reduce the size of the traces, going from memory the smallest wires were around 30um 5-10 years ago and now days it's around 3um.
Personally I'm looking forward to when we get to the stage of stacking memory (cache) on-top or under the silicon doing the work using TSV's, although that maybe head in the clouds thinking. :)
My worry with that is that at the high end CPU design has a large element of heat and power management. Stacking something on top of the CPU stops the heat getting out, under stops power getting in. We already have mobile/laptop centric chips at the expense of desktop performance, I fear that would be another example.
Yes re: the heat getting out but no re: the power getting in, that's what TSV's are for.
I should note it's not something i expect to see happening soon (next decade) but it's something I'd like to live long enough to see, there's a lot of barriers/problems to sort out before that happens though.
Shrinking nodes only get you so far, even Gordon Moore hypothesised that there would come a time where we'd need to start building up and out because eventually making things smaller only gets you so far, i mean he was out by a few decades but he can't get everything right. ;)
Warm silicon is not a superconductor ;)
Any additional layer or transport is going to have an impact on power transmission. That's basic physics. How significant that impact is will vary depending on what the intervening layers are doing, and it may be that you actually end up with the stack being more efficient overall because you're using shorter TSVs and transports, but to claim that stacking won't have any impact is just naive...
Phew! Good job i didn't claim that stacking won't have any impact then. ;)
Perhaps you'd like to explain then as saying "the power getting in, that's what TSV's are for" doesn't seem to be saying or even implying that it "won't have any impact".
You were explicitly disagreeing with DwU's point that sticking chips below the CPU silicon would interfere with power delivery. You clearly implied that using TSVs would resolve the problem. You failed to acknowledge that there would be any impact.
If you're only partially disagreeing with someone, it's often a good idea to expand on what you think the situation is, rather than just saying "no"...
No, i was disagreeing with DwU's point that "Stacking something on top of the CPU stops the heat getting out, under stops power getting in".
If you were being pedantically literal with his statement, you'd point out that silicon isn't a perfect insulator and heat would happily pass through an additional layer of silicon with appropriate cooling. Sure, it wouldn't be as efficient, but an extra layer of silicon on top of a CPU does not "stop heat getting out".
If you're going to read the statement literally, disagree with both points. If you're going to read it as hyperbole (as I did), disagree with neither point. Agreeing with one and disagreeing with the other makes no sense.
Is it that you just have some axe to grind with me personally? Because i know you've read my reply to DwU so you know i said "Yes re: the heat getting out but no re: the power getting in, that's what TSV's are for.".
To make that clear and hopefully circumvent further ad homenie attacks such as saying I'm being naive, that there's something wrong with the way i communicate, and that I'm pedantically illiterate allow me to explain: Heat is linear, power is not. So when DwU said "Stacking something on top of the CPU stops the heat getting out" saying yes is entirely correct as the heat at source would not be the same as the heat at the external surface, when DwU said "under stops power getting in" it is also entirely correct to say no as power is a binary, you either have it or you don't.
Is that clear enough for you or would you like to attack me personally some more while completely ignoring someone who said that what you said is "purely a figment of your wonky imagination" and that they "don't need you to tell us that".
This isn't an attack on you personally - I'm pointing out that the way you originally made your point did not clearly communicate your intention. There appeared to be a clear implication that additional silicon below a CPU die would not impact power delivery.
As it happens, now you've clarified what you were trying to say I also happen to disagree with your point. In both cases the additional silicon will add resistance to the movement of either heat or power. It will be harder for heat to escape, it will be harder for current to get in. In neither case will the movement either be completely stopped, or completely unimpeded.
ADDENDUM:
I hadn't actually seen that reply - I have a limited amount of time for forums and follow some threads closer than others. Now you've brought it to me attention I'll go and have a proper look...
And that's why i said that's what TSV's are for, they do not add resistance to the movement of power anymore than traces, power lines, or bumps do, whereas *AFAIK there's no way you can't add thermal resistance when you increase mass.
* I know there's been laboratory tests of exotic types of cooling between transistors but i don't think anything has reached production.
No, but they still add to the resistance - it adds at least one more set of bump and transitions, which means you get power loss over those additional components. So either you have to drive more power to the socket, or use less power in the CPU. In pretty much the same way that an extra slice of silicon means you get increased thermal resistance, so you have to use beefier cooling to maintain the temperature gradient and get heat away from the CPU.
You seem to be convinced that the thermal effect will be significant while the electrical one won't. I'm not so sure...
Yes but any electrical connection from one point to another adds resistance, traces, power lines, and bumps all add resistance and they're all accounted from when designing the power requirements, however that's besides the point as the original proposition was that it stops power getting in, not that it increases resistance.
Increased resistance, not that that's typically what happens when using TSV's as resistance actually goes down due to the shorter distances involved, however increased resistance can and has been taken account of when designing your power delivery circuitry for decades.
Whereas you can stop, or at least drastically reduce, the escape of heat to such a point where it causes failures.
As I said, I read that comment as hyperbole. I'm pretty sure DwU wasn't saying that it's impossible to get power to a CPU that's stacked on top of another another piece of silicon, he's not an idiot...
You can engineer around heat transfer as well though. I still don't understand why you want to treat the heat problem differently...
Anyway, it's all about those engineering compromises. If you have chips spread over a wider area you can use larger traces which have lower power loss. Once you concentrate all your power delivery into a small area you start making compromises on what can happen - you have to use smaller traces and bumps which have greater power loss, you have to add additional bumps and connections between dies which increase power loss, and you cram a lot more current through a smaller area - which increases power loss. It all adds up.
And while you can engineer around some of that, ultimately you can't beat physics, which means the end solution may well be designing chips that run at lower power and generate less heat - which is exactly what DwU said in the first place.
Blimey, I know you have to be careful what you say on the Interwebz but this surprises me. Using the word "stop" was with hindsight not optimal, but if I wanted to say it was a perfect insulator I would have been a lot more wordy.
Really, it was a throwaway comment that I could see issues with using stacking with a CPU on desktop machines which wouldn't be an issue on laptops. Consider the grief Intel have had in recent years because the thermal compound they used wasn't as good as a solder when both were designed for thermal conductivity. So how well is introducing a semiconductor layer between the CPU and heat spreader going to go?
I wrote a big long thing on power delivery here, but now I've deleted it because I just don't have the time to get into another discussion. But really, power traces are considered inductors, they are far from a binary issue.
("Post Quick Reply" sometimes seems such an inappropriate button name :) )
Edit: Mostly my thoughts were that laptop users wouldn't see an issue as at 35W none of this matters let alone the 15W you often get in laptops. But I prefer desktops and don't like anti desktop tech.
And IMO i treated it as a throwaway comment, hence why i kept the initial answer brief, but apparently scaryjim took exception to my yes/no answer and said that i really needed to work on clear communication and that i was naive.
Seems i can't win either way, one of you berated me for a being too brief and the other for being overly specific. :wallbash:
Speculation that the ryzen 3xxx series will launch on the 7/7, for me that makes a ton of sense;
a)allows for 1x and 2x inventory depletion.
b) allows for 8/12c TR inventory depletion.
c) limits chip cannibalisation.
Also it allows Rome to come out before that. Plus it gives them time for another spin to iron out bugs. More so on the Io chip than anything
Whelp, I'm up for a new CPU. With the imminent launch of zen2, my plan is to go with a zen-based athlon for now then upgrade (either to zen 2, or a cheap zen+) in a few months. I'd like the stand-in to provide similar performance to my current i5 (haswell 4C4T), and be as cheap as possible (duh) - do you guys think a 200GE would cut it? "Similar performance" means not tanking fps in not-brand-new games (doom, unmodded skyrim) - it'll be a bit slower (similar IPC, less speed), but the same number of threads (and older games probably don't multi-thread all that well)
I'd spend a little extra and get a Ryzen 3 1200 because 4C4T rather than 2C4t should give a significant performance boost in newer games. https://www.amazon.co.uk/gp/offer-listing/B0741DN383/ Used ones show up on Amazon warehouse for <£50 sometimes.
I was in a similar position a while back. 200GE is 4 threads not 4 cores, so I suspect that isn't up to the task.
4690K is still a pretty capable chip. I'm using a 2200G which is quad core and seems reasonably quick but in the VR headset just runs out of threads.
I can try it in flat screen Doom when I get home, but I suspect it will be fine. It handled Elite in 1440p, levelling up a WoW character up to level 20 which are quite modern. Can't remember what else I have played on it, but it hasn't stuttered yet on a standard screen. I baulked at £80 for the 2200G, but when I upgrade my main rig it would be easy to re-purpose.
If I were choosing again, the 2600 at £130 is a stonking deal and I would probably just go for that. Again, a capable chip that can easily find a new hand me down home, and would mean I could wait a bit for release day prices to drop and make sure the BIOS bugs are shaken out before getting Zen 2. Even this close to Zen 2 release I am slightly twitchy to buy one so I can get the VR headset out, but it has been a bit of an expensive month.
Good idea - there was a new one for £53 with p&p, so that's a pretty cheap upgrade on the 2C athlon.
Going straight to a high end ryzen is tempting, but I'm fairly certain that zen2 will be worth the extra outlay on the stand-in CPU (or will cause price drops in high-end zen+ enough to make up for the extra cost). I'm happy with the performance now, so if the stand-in matches my i5 then I'll have plenty of time for zen2 to stabilise before buying :)
When I crunched the numbers for my step-son's computer 18 months ago istr that a Ryzen 3 1200 had better performance than the i5 3570k, which was the most likely upgrade option on his existing platform - which is why I opted to do him a full rebuild rather than a quick upgrade.
Worth remembering that all Ryzens can be overclocked on suitable motherboards (and since you're thinking Zen 2 I'm assuming you'll go for a higher end board), so if you're up for a bit of tweaking you should get very close to the stock 4690k, and even at stock you'll find you're not losing that much. I went for the 1300X for my step-son because he's not an overclocker...
Yep - Asus TUF B450M-plus gaming. Seems to be one of the best available in MATX (except the -pro model, but that doesn't have the GPU in the first slot which is not optimal in my case).
The cooler doesn't look like much next to my old intel stock cooler - both around the same heatsink dimensions, except the intel one has no nice-looking shroud and braided cable, but does have a cup-shaped bit of copper in the core, and is intended to cool 91W of heat rather than 65W. Mounting the AMD one was a bit disappointing - the screws were hard to line up with the backplate, and they squeaked a lot as they went in, and you had to remove some plastic from the motherboard that seems to only be used to mount the top end wraith cooler (surely those users would want the better mounting pressure that comes with screwing together bits of metal?). There was also a very thick layer of thermal paste on the heatsink, so I might try a better application of paste later to see if it improves matters.
One downside of the 1200 over the 200GE - first gen ryzen ram compatibility! I forgot to check, so the ram I have is on the approved list for second gen ryzen but not first. I'm fine if it doesn't run at the full speed (still an improvement on 2133 MHz DDR3), but hopefully it boots tomorrow!
That's interesting, though I'm not sure where the APUs stand in that as the cores are supposed to be 1st gen but as a later product they may well have tweaked bits on it, but you probably wouldn't have been any better off. I'm running my 3200 ram at the top rated speed for the 2200G APU which is 2933.
I'm running my 3200 ram at max speed the 2200G is rated at which is 2933.
Happy booting, hope it goes well.
All booted fine, other than my wifi card deciding it didn't like its new home (probably because it's an intel chip). Ram decided to run at 2.4 GHz, which is fine for now
The boost behaviour is not what I'm used to. My old i5 would happily run at the full 3.9 GHz on all cores without overclocking, and at idle would clock down to ~800 MHz. The 1200 will only run at the 3.1 GHz base speed on all cores (which is expected, as it's a bottom rung part), but at idle it only drops to 2.6 GHz or so. I think it's using less power at idle though - previous idle temps were 36 C with a half-decent aftermarket cooler, but now it's just 28 C on the stock wraith stealth :D That little cooler has impressed me with what it can handle, and under load it's always under 60 C (compared to the intel chip hitting 79 C, with an aftermarket cooler)
I only ran 3dmark benchmarks, but in those it's impressed me - the CPU performance suggests than the 1200 beats haswell clock-for-clock. It's a bit slower in the CPU part of the tests (5% across the 3 versions of firestrike, 10% in time spy), but that's with the i5 running 25% faster! If I can match the 1300X clocks when I get around to overclocking then I should see a clear improvement with ryzen.
I also took the opportunity to re-paste my GPU, and saw a 4 C reduction in temp under load combined with a 600 RPM reduction in fan speed, so it's been a pretty successful rebuild :)
Ryzen can idle below 1GHz. I don't know if it is still the case but I know CoreTemp and the Windows task manager used to incorrectly report core frequency, and usually displayed the base clock. Other hardware monitors could report the actual clock speeds though. You might also need to check your power plan (again an old problem that I think Microsoft has fixed) and see what the minimum CPU speed is set to.
Maybe your motherboard is also keeping your CPU speed up so check if there are any enhancements enabled?
Please advise me folks (and hello after a short period abstinant)
I have parts for a desktop build for my front room (I live alone) including :
a no MSI X470 GAMING PLUS ATX from Germany (had to order 4*SATA for it as someone had removed and returned. the product us.
)
Advanced Devising Ryzen 5 2400G
ASRock MicroATX Motherboard (B450M-HDV) - I don't know why I bought this it's still boxed and I should move it on. Prime fever maybe!
new pre#tested though as yet unfunctioned! here's TEAM GROUP T FORCE VULCAN TUF 16GB DDR4 3600 (19 19 19 39 1.35V) which cot £121 inclusives durings an 3/2 A.Di 2 19
I have recently got after some money worried 3 QUADRO P383 which should manage 1080p @ 75 or maybe 90 hz if I am lucky with Win10.
Should I sell the boxed new CPU for a 2 or 3 series Ryzen chip? My main desktop runs an 1700 @ 3.9 (while it used to do 4.05 GHz * 8 2 core. thread..()) with FlareX 14 3200 memory whilst a B350 Gaming Pro MSI offering (dunno which revisions).
Thank you and it's coming too a : 1 am on 14/05/ 19
Task manager seems more responsive than ryzen master - the AMD one only shows variation from 3.4 - 2.8 GHz, and seems to update slower. I didn't notice any motherboard enhancements on in the bios, but will have another look
DDR2 ram on the GPU :crazy: I'd recommend just using the V11 on the 2400G, both of your motherboards have DVI and HDMI
Those Quadro cards are the professional variant of the GeForce 6200 - an entry level DX9 card from 2006. I've got 10 year old motherboards with better IGPs. I'm a huge fan of retro tech, and even I would put one in a computer I actually wanted to use.
The Ryzen 5 2400G is essentially a Haswell Core i7 with a Radeon RX550 bolted on - it's a pretty powerful package, and I can't see what you'd be doing in your living room that would need more CPU. Just slap it and the memory in whichever motherboard you prefer and you're good to go :)
I'm really surprised no one's posted info about Computex and Zen 2. https://www.anandtech.com/show/14407...e-40-coming-77
Zen 2 is looking to be pretty strong so far!
And that L3 cache! 32MB for the single Chiplet CPU's!
I think I have smaller SCSI hard disks than that in the cupboard :D
Motherboards are being shown, it sounds like reviewers are under NDA, so I guess we are just waiting for proper reviews to come out. Oh, and for a retailer to take my money as I am bored of my 2200G now, it's been a cracking little chip for the money but I want the get back to playing VR.
It has been a long, long time since I actually got excited about anything hardware related. Recently it has been a matter of resenting having to pay so damn much just to keep pace (i.e. GPU upgrades).
The news Ryzen chips, PCI-E 4 and their associated M.2 SSDs have changed that and I actually have the urge to upgrade for the first time in ages.
Since the last update, I've been getting some horrible lag in games which seems to correspond to loading new bits of a map. It was there initially after my upgrade to 4K gaming but it has gone from twice in a 30 minute level to once every 30 seconds and it's annoying. From the news articles, I suspect this is due to yet another performance hammering Intel vulnerablity patch. It has got to the point where I've now applied the overclock I've been holding back on and I'll see if that helps.
In the mean time, it is definitely time to be considering a new generation Ryzen, a new mobo, an M2 SSD that has these insane PCI-E 4.0 speeds and so on. The only thing is I want to be keeping my old PCI sound card which was extremely expensive and is still very good. The new Ryzen chips with all their cache are seeming like a real, proper step up and on top of that they are at a reasonable price. This is what Intel should have been doing but have been holding back on in their arrogance.
I hope they get pasted for it as it'll perhaps stop them being so damned arrogant in the future. If they had been sandbagging and had something useful ready for release it would be different but it's clear they didn't even bother doing that.
The question will be what to go for - mid range again or push the boat out for something pokey. I await benchmarks with hairy palms.
Similarly to the above, I'm eagerly anticipating these new chips. What I have begun to notice though is the proliferation of motherboards with 8+4 pin EPS sockets - these started around the X470 gamer type boards I think, but look like they will be present in X570 too.
This worries me, mainly because I don't have a route to get +4 neatly from my PSU, but also because that's suggesting really extreme power draw possibilities.
Are they adding the cost of the connector just on the off chance you want to LN2 overclock a 3900X? Will only providing an 8pin reduce the number of VRM/phases delivering power to the chip?
It could also be to supply 75W to each of the PCIe x16 slots on the motherboard. My X470 board has one 8 pin power socket, which seems iffy for feeding 3 GPU slots and 105W CPU. Though I am currently running one PCIe GPU and a 65W APU so I'm not exactly stressing over power limits :D
I'm guessing USB-C will need a 12V feed as well.
I suspect that the lower end boards (B550 maybe?) will not have these connectors as they probably won't be so overclocking focused.
I'm also eagerly anticipating these chips but I have a problem. I can't really justify replacing my current system as although it could do with being faster at certain very rare points, they are rare and 32GB RAM that I would need makes it too pricey for my to just buy one any way. Plus I'd need an M.2 SSD just because there will be a slot for one on any motherboard I get. Thus it must be filled with an SSD with more performance than I need.
A wider design will always need more power when pushed to the limits - if the chiplet tops out at similar power to the current 8C die when overclocked fully, then you'll need twice the power to run two chiplets at the max. As watercooled said the TDPs are nothing unusual, so there shouldn't be any power issues unless you wanted to run an extreme overclock.
In other news, my R3 1200 has surprised me. My RAM isn't on the 1st gen compatibility list, but it happily runs at 3 GHz without issues. I guess it must be later BIOSes improving things? I always figured the silicon was at fault in first gen ryzen, but I guess not
You probably don't notice when swapping's occurring TBH :D
The problem I have is that I cannot allocate more than my physical RAM to VM's so 16GB+ fast SSD isn't an option. Plus I wouldn't do that because I couldn't bring myself to pay to "upgrade" my system and have part of it downgraded as a result.
All I'll do is wait until my system's performance affects me enough to bother me to spend money on upgrading it. At a guess the upgrade of the "guts" will be around £600 including an M.2 SSD
OK, interesting video I stumbled across this morning: https://www.youtube.com/watch?v=qszxxIumJOQ
He explains the dual 8 pins connectors are purely for CPU, there is a separate 6 pin power (in a bad location :) ) for extra GPU power which usually comes from the 24 pin main connector. He also gives stats for the connector, that 8 pin can apparently take about 50A which at 12V is around 600W. I think for most of use that leaves plenty of headroom without touching the second 8 pin :D
That motherboard is a bit overkill! Not just 8+4 for the CPU, but 8+8. I'd love a similar analysis for the slightly cheaper range.
I've been waiting for Zen 2 to upgrade my aging i5 2500K CPU/motherboard/RAM combo. However I read on Toms Hardware that AMD's PCIe4.0 chipset has increased the chipset's power draw from 3.5W to 10W. According to the article, Motherboard manufacturers are going to utilize more expensive power circuitry design in the X570 range and as a result these motherboards will be more expensive, in the Z390 pricing range or maybe higher. Source: https://www.tomshardware.co.uk/msi-a...ews-60894.html
If building a Zen 2 rig around a Zen 2 3600 and X570 board will be considerably more expensive because of this then perhaps building a Ryzen 5 2600 + X470 board is a solid budget choice at the moment?
If you can wait, I'd wait for Zen2 reviews to consider the 3600 and X470 (or B450, if you can live without SLI). It'll likely cost more than a 2600, but the 2600 will only get cheaper (especially with the claimed performance). No PCIe 4.0 on a 400 series motherboard, but other than that it'll perform the same
I wonder what the pricing will be like for the reminder of the chipset range, it would seem a bit unnecessary to have an overkill VRM on a board not intended for overclocking.
It really depends on your budget.
TBH I'm not that concerned about the increased power draw in the chipset, it's on par with the power used by all the RGB junk and I suspect only happens when you plug in all the PCIe cards that I don't own (yet) :)
The cost does sound significant though, so I suspect I will stick with my X470 board for now. Maybe that means I can't have the 16 core, but I can't afford one of those anyway so no loss. But as others have said, the reveal should be under a month now so I'm not making any rash decisions.
Has there been *any* news of other chipsets yet? I've only heard of X570, which makes me wonder if there is still a ton of 4x0 based boards waiting to get sold off before they will release lower end 5xx series boards.
I don't recall reading about any but I've not been paying all that much attention to be honest. FWIW though I can't see a 400-series board being an issue, I don't imagine most people are struggling for PCIe bandwidth on that platform anyway.
The *low* end didn't get a 400-series board - there's still no replacement for A320 at entry level.
I'd seriously question whether B550 is necessary - the only thing X570 really brings to the table is PCIe 4, and that's not exactly mainstream. At launch you'll already have the choice of X570, X470, B450 and A320 motherboards. I find it hard to believe there's a market out there of people who desperately want PCIe 4 but want it on a no-frills entry-level motherboard? If you're in the market for a mainstream motherboard surely the lack of PCIe 4 isn't going to be a deal-breaker for B450?
Going on what people have said they seem to have put more effort into X570 boards so people expect they'll be able to clock higher on both the CPU (better VRM) and RAM (better trace layout), how much better though remains to be seen, i guess only those with deep pockets will be willing to fork over an extra £100-200 for maybe an extra 100Mhz.
I was considering an X570 and a Ryzen 7 3800X but now I'm wondering if i wouldn't be better off dropping down a tier.
I think having PCIe4 traces from the CPU to an NVMe M.2 slot and GPU with a decent but not optimised for lunatic LN2 overclocking VRM would seem a good market. The B450 chipset would allow that, but it would be nice to know that it is PCIe4 enabled. I guess like with AM3 we got lots of "USB3" motherboards we might start seeing B450-PCIe4 boards turning up if we don't get a proper B550 some time soon.
X570 just seems OTT for most users, though frankly I like seeing AMD aiming high for once.
It might be that they're expecting users to overclock a poor silicon 3800X - which might have been binned poor on thermals/power but able to slurp it to high levels provided the motherboard is beefy enough.
Would they be keeping all the best chips in stock for the few months between july and september?
If they just cream off the very best silicon it might take a few months to get enough for a launch, and they would have been stockpiling for a few months already if most of the line is launching in a few weeks.
On the other extreme, it usually takes a few months before they have enough die with a few dead cores to know what to release as salvage products.
Also it's worth remembering that Threadripper was meant to be the top … was it 5%? certainly low single digits … binned dies, which is why they could run multiple dies at high clocks in a "reasonable" "desktop" TDP, and TR didn't release until well after Ryzen in both 1st and 2nd gen products.
Of course, with the chiplet design they'll be making so many dies per wafer, and such small dies, that I suspect they'll have uncommonly high yields compared to modern monolithic CPU designs, allowing for tighter qualification for particular bins. I'd tend to support kalniel's speculation that the 3800X will be binned for ability to reach very high clocks almost regardless of TDP/voltage, while 3950X will be binned for hitting target sustained clocks at low voltage. AFAIK binning nowadays is much more complex than "must hit X GHz at Y volts" pass or fail....?
I've not got the time to find the link but IIRC AMD reported they're getting around 70% yields on 7nm.
That's much higher than you'd typical get when moving to a new node, i guess it's mainly because of the small die thing scaryjim mentioned.
IIRC yield tends to decrease with something like the square of die size*, so having a multiple, smaller dies should be massively beneficial in terms of yield and binning. TBH I'm surprised it's not higher than that given they have some experience with 7nm already and the node isn't brand new, but it's still early days for that product I guess.
*Of course that's an over-simplification of a fairly complex matter, but it's a rough estimate of yields for 'perfect' dies due to defect density. In reality there are generally many ways to repair/salvage dies.
Yield decreases to the power of the die area. If there's some probability that a given square mm of die doesn't have a defect, and a perfect die needs to have no defects, then P(perfect die) = P(no defect on a given square mm)^(die size)
Apologies for posting another Level1Tech video but Wendell sat down and had a chat with Ian from Anandtech that i found interesting.
https://www.youtube.com/watch?v=cTmnyOZ0pE4
Yeah that's a far more realistic approximation, the squaring didn't sit right with me though I've definitely read that quoted a few times in articles, just never actually sat and thought about it properly.
The point I was aiming to make though, is it's not a linear decrease with die area increase, and as such separating them out into chiplets should in theory lift yields/help binning substantially as others have said.
Someone's posted a very nice geekbench score... (still up on the geekbench results browser, so not faked, but probably overclocked).
AMD Matisse, 3.3ghz base, 5.2ghz max. 16 core, 32 threads... Ram at a speedy 4266mhz too..
Single thread: 6714
Multi-thread: 64953
https://browser.geekbench.com/v4/cpu/13669931
any news yet on the bundled coolers with Ryzen 3000 series, if at all ?
https://www.amd.com/en/technologies/cpu-cooler-solution Scroll down to `BUNDLED THERMAL SOLUTION` and you should see them all listed there. Last time I checked there was some level of inconsistency between the product page and this chart.
Bits'n'Chips say they have information that Zen2 chiplet yields are now 'over 85%':
https://www.bitsandchips.it/english-...-very-good-job
So putting that into a yield calculatorQuote:
According to our sources, the yields of Zen 2 are enhancing quickly. Three months ago we wrote that Zen 2 yields (100% fully working chip) were about 70%. Today, yields are about 85%!
Zen 2 yields are still a little bit lower than Zeppelin ones (Today at +90%), but at this rate Zen 2 will be inexpensive to produce. TSMC 7nm yields are near 16nm yields (Source), and 7nm wafer cost is now under 10k Dollar (IBS Research).
http://www.isine.com/resources/die-yield-calculator
along with Navi's (and Polaris with an estimate of $4,400 per wafer from around the Polaris launch), we get something like this:
https://i.imgur.com/rhimoeZ.png
Obviously Zen2 has a the IO die too and the new mixed node packaging might cost a bit extra too, but not bad.
As for Navi, it is a lot more expensive than what Polaris launched at, assuming that wafer estimate is anywhere near to being correct - I could only find one place which mentioned it around that time, and that was more TSMC whereas AMD might well have had a better deal from GF (or if they didn't use wafers they'd have to pay anyhow due to the WSA).
No idea what GDDR6 costs, but compared to Vega the whole card must be far cheaper to produce.
Does the 3600x justify the $50 increase over the 3600?
Very interesting, any idea if high yields correlates with better quality. I'm interested in whether future ryzen 3000 chips will have better overclocking potential than the launch chips as we have seen this in the past.
I couldn't find a X570 motherboard thread so I'll post this hear..
https://www.youtube.com/watch?v=qk3PD-4zPN0
The TLDW version is he tested the power draw of the X570 chipset and found that a PCIe 4.0 NVME drive results in the same power draw as a 3.0 device, even though he was confused by what he discovered i suspect he got caught up in the rumor that its increased power requirement was due to PCIe 4.0 when personally i believe it's actually down to how many devices you hang off it.
Interesting, very good (but not unexpected given area) yields for Zen2 if true. I assume the Polaris comparison is using release date yields/cost? Or are they really suggesting that defect density on 14nm *right now*? I know they're likely only ballparking it, but still impressive it true - 7nm is still quite new!
I've just watched that myself. The way I interpreted it, the chipset may be drawing more power because of the PCIe 4 capability and PCIe 4 link to the CPU, not just because of active PCIe 4 links. It would seem there's room for improvement though, e.g. I wonder how much is being properly gated when unused?
You mean the increased power draw at idle between the X470 and X570?
I get what you mean if so but i think that could be down to X570 just supporting more connections, i just tried working out if it did but got totally confused. :)
Yeah I'm referring to idle draw mostly. Only speculating though.
I suspect it's just that the x570 die is simply identical to the I/O Die on the Ryzen 3000 Processor - i.e. not optimised for the use as a chipset and a bit of a power hog with the bare minimum turned on to operate as a north/southbridge. I thought it a bit off but for speed to market I guess it makes sense. It's successor will probably be made on a similar process but significantly lower TDP.
The improvement in power efficiency may be more than it first appears, as the X570 boards seem fairly power hungry: https://www.extremetech.com/computin...pu-comparisons
I'm not sure how much of that is down to the chipset alone as the article claims but I very much doubt the chipset itself is responsible dissipating anywhere between the 30-50W seen in the difference between X470 and X570. Maybe the VRMs etc are partly responsible?
Edit: Hmm, I'm not too sure about their x570 results though. Hexus do whole-system power measurements and they seem to agree with other articles I've read using the 9900k as another reference point. x570 power seems anomalously high for extremetech?
I had to go and read the X570 article when I read this: hadn't realised they'd done that.
Presumably this means the IO chip has the capacity to plumb out all those extra USB and SATA ports too - I assume the reason it doesn't is down to pin compatibility with previous desktop generations.
It may also be the reason AMD have publicly stated that Zen 2 APUs won't be chiplet-based: if the IO chip is relatively power-hungry it'd be a very bad fit for a <= 15W processor....
Something else I've just noticed (and found interesting): AVX performance seems very good with Zen2, and it doesn't seem to have much of an impact on power consumption. Intel CPUs seem to draw noticeably more power under AVX2 workloads as seen here: https://www.tomshardware.com/reviews...ew,6214-3.html
Bear in mind that the 3700X is *faster* at y-cruncher and on-par for Handbrake vs 9900k as seen on page 12 of that same article.
Wild Threadripper 3000 speculation for your consideration:
We already know that Ryzen 3000 will cover (at least) 6/12 - 16/32 configurations. I'd lay a small amount of my own money on the next gen APU series covering 2/4 - 4/8. I doubt we'll see a Ryzen 3000 CPU with less than 6 cores - the 3400G is already out there @ 4C/8T and I don't think it makes sense to overlay the product lines that much.
With the chiplet design, I'm not sure repurposing Epyc IO dies for TR makes much sense - with Zeppelin all that IO was bundled with the cores so you had to have it in there if you wanted the cores, but now there's just no need to waste half your silicon. So, if we have a specific IO die for TR - quad channel memory, 64 lanes of PCIe 4, presumably - how many chiplets does it take? More than 2, obviously, and I'd imagine at least 4 so they can match the current line up @ 32 cores. But will they stop there?
Also, where will they start? With X570 potentially supporting 3 or 4 NVMe drives (or 4 PCIe 4 x8 slots), is there any need for 16 core Threadripper? Could they start the line up with an 18C variant (i.e. 3 chiplets each with 6 active cores) to differentiate the platforms?
Any thoughts?