Features - Roy Taylor: AMD Radeon GPUs remain unsurpassed

[DanceswithUnix]

There exist a whole range of FPGAs, yes, from cheap to expensive. However, there are G-sync monitors handling 2560x1440 at up to 144 Hz. At 8 bits per subpixel, that's up to 12,740,198,400 bits/second (12.7 gigabits) ignoring overhead, blanking intervals, etc.

So in total about the same as one direction of a single 10GbE network port, that isn't very impressive is it.

G-sync is just doing a bit of buffering. Buying a bigger FPGA doesn't automatically make the system faster unless you are packing the part so full that placement is having difficulty, it just means you can do more stuff in parallel at the part's clock speed.

There is another direction to look at this though. Suppose you are designing the next panel driving asic. If things just fall into place and adds nothing beyond some design time, then it will be worth doing. But what if it does make the finished product more expensive? Now customers can either buy your monitor, or they can buy an opponents who didn't bother adding this stuff. Let's say it adds a fiver, then a gamer might think that is a no brainer and you made a sale, but someone outfitting 200 monitors in an office doesn't fancy paying an extra grand for something that doesn't help in PowerPoint, so your opponent just made 200 sales. I have no idea whether Nvidia are demanding any license fee for G-sync, but if they do then I expect them to end up as popular as Firewire for exactly the same reasons.

[crossy]

I'd forgotten about this thread and just came across it again. Wasn't sure whether to reply but...



Fair enough, I suppose it was a bit of a cheap shot but don't make the mistake of assuming my comment was fanboy-ism on my part. I would have said something very similar had it been an Nvidia PR guy going on about a grass simulation
Also not my intention to demean the work of the people who work on the tech, I mean I'm glad their working on increased realism I just don't see using grass or hair as a selling point swaying many people.

You're right - I had assumed (wrongly) that you were one of those rabid green-in-the-veins NVidiots. Sorry about that. Totally agree though, that while sim-grass and TressFX are interesting from an academic point of view, your teen-gamer isn't going to be much bothered.

[watercooled]

Thankfully it seems (though I stand to be corrected) that both TressFX and the SomethingWorks effects are at least cross-platform so don't cause vendor lock-in.

Now I wonder if the PhysX CPU code will be brought into this century, or run over something like DirectCompute (rather than CUDA) like the other SomethingWorks effects?

[edzieba]

So in total about the same as one direction of a single 10GbE network port, that isn't very impressive is it.

Have you taken a look at the cost of 10GigE networking equipment recently? It's a couple hundred quid for a reason.

Buying a bigger FPGA doesn't automatically make the system faster unless you are packing the part so full that placement is having difficulty, it just means you can do more stuff in parallel at the part's clock speed.

DVI (and DP) are serial links. They transfer pixel data in a single lane. You cannot paralllise reception of it because there's only the one stream, so that data has to be handled as it arrives. That is why high-clocking FPGAs are required. You don;t get 'better performance', it's simply a requirement of a minimum performance to do the job.

There is another direction to look at this though. Suppose you are designing the next panel driving asic. If things just fall into place and adds nothing beyond some design time, then it will be worth doing. But what if it does make the finished product more expensive? Now customers can either buy your monitor, or they can buy an opponents who didn't bother adding this stuff.

Hence why integrating DisplayPort Adaptive Sync is an optional component of the DP standard, to enable price stratification. In all likelihood, all new display controllers from this point forward will contain the circuitry required to handle both DP Adaptive Sync and G-Sync on-die (because it is a LOT cheaper to build one chip line for a slightly larger chip than to run two chip lines, and the two do the same thing so share the majority of the circuitry), and price stratification will occur by not populating ancillary components needed for asynchronous refreshing.

[watercooled]

Have you taken a look at the cost of 10GigE networking equipment recently? It's a couple hundred quid for a reason.

And yet existing DVI, DisplayPort controllers are cheap. Cost isn't just tied to speed. For internal interfaces (since the external transport is already handled by the existing display interface for G-Sync), we have PCIe, HT, QPI, CSI; this sort of bandwidth is nothing unusual here.

DVI (and DP) are serial links. They transfer pixel data in a single lane. You cannot paralllise reception of it because there's only the one stream, so that data has to be handled as it arrives. That is why high-clocking FPGAs are required. You don;t get 'better performance', it's simply a requirement of a minimum performance to do the job.

Then why not use a smaller, higher-clocked FPGA? Just because something arrives in a serial stream doesn't mean it can't be handled in parallel in the processing logic; and in this case where it's going to be buffering, it's also highly pipeline-able, which is another way of making use of more gates on the FPGA.

[edzieba]

And yet existing DVI, DisplayPort controllers are cheap.

Because they#re commodity ASICS. FPGAs aren't. Hence why FPGAs that can do the same job are expensive.

Then why not use a smaller, higher-clocked FPGA?

Because it is already using the smallest FPGA that can do the job. The whole POINT of asynchronous refreshing is to display frames as they're produced (and output), not buffer until the display is ready. This means that you need to process and ready for panel update the incoming data as it arrives. This adds a minimum speed constraint on the FPGA used to implement it: it needs to be able to process each pixel as it arrives.

[watercooled]

Because they#re commodity ASICS. FPGAs aren't. Hence why FPGAs that can do the same job are expensive.

I may have misunderstood that discussion thread then, I thought it was about implementation cost in ASICs for some reason.

Because it is already using the smallest FPGA that can do the job. The whole POINT of asynchronous refreshing is to display frames as they're produced (and output), not buffer until the display is ready. This means that you need to process and ready for panel update the incoming data as it arrives. This adds a minimum speed constraint on the FPGA used to implement it: it needs to be able to process each pixel as it arrives.

The point was that you can also get high-clocking FPGAs with less gates and IO - just throwing more silicon at a problem doesn't help unless it's being used for something. And since panels don't have infinite refresh rates, buffering is still a necessity.

[whatif]

Even if you had a video interview, the replies would have still been similar.
As a corporate vice president of a global company, he undoubtedly would have a high level of responsibility towards the company. So of course he would talk up the company.
In no way am I saying anything about the content he gave above.
It is just like getting a media release off a politician in answer to some questions. There will always be spin.
Everything needs to be taken in context.
As for that show "Everyone Loves Raymond", personally I hate it and never watch it.

Besides, I am amazed at the level of debate reached in these forums over a article with no real new content or information. Just spin.
Clearly, like there is more than one side to a coin, there is more than one opinion here.