Intel Sunny Cove next generation architecture unveiled

[HEXUS]

IPC, efficiency and features boosts coming to Core and Xeon processors late 2019.

Read more.

[Tabbykatze]

A new 3D packaging tech dubbed 'Foveros' was demonstrated by Intel. Foveros is said to combine high-performance, high-density and low-power silicon process technologies and will afford "tremendous flexibility as designers seek to mix and match technology IP blocks with various memory and I/O elements in new device form factors," according to Intel.

So they're moving to Chiplets like AMD. They've even not tried calling their 22nm I/O die an I/O die like AMD has. It sounds like Intel had a shelved chiplet design, saw what AMD has done and has unshelved it because if AMD hadn't done this with the Zen 2 lineup, they might have continued with the standard monolithic approach.

Intel's Sunny Cove CPUs not only increase performance per clock and power efficiency for general purpose computing tasks but include new features to accelerate tasks such as cryptography and AI...

The first Sunny Cover CPUs will be released in H2 2019 and will boast "reduced latency and high throughput, as well as offers much greater parallelism". Intel thinks gaming, multimedia, and data-centric applications will all benefit from Sunny Cove.

So Intel have been forced to move away from their single core focus and have had their hand forced in making a new architecture.

Coming to 10nm Intel processors next year is the latest Gen11 iGPU with 64 enhanced execution units, more than double previous Intel Gen9 graphics (24 EUs). Intel asserts that these GPUs will break the 1 TFLOPS barrier (and thus a similar TFLOPS perfromance to the AMD Radeon Vega 8).

That's pretty impressive for integrated graphics. Would really like to see an AMD 3xxx APU versus a gen11 Intel integrated solution with price/performance metrics (which is what is the primary consideration for these types of systems). If it is low power and can perform that well, Intels integrated graphics will still stay relevant.

Intel restated that it is pushing ahead with plans for a discrete graphics processor for launch by 2020.

Not much about the dedicated side as expected, i'm sure there'll be more info in 2019 as it draws closer.

However, average development expectancy for a GPU architecture by Nvidia and AMD has been over 3 years. To go from absorbing GPU development talent then releasing a GPU in 3 years from a company that only deals with low power integrated solutions does concern me.

I hope Intel isn't just thinking they can throw excessive money and manpower at a problem and it will suddenly create a working product. I look forward to further updates!

[876HX]

"10 petabytes of data within 10 milliseconds to every person" what this really means? data transfer speed inside the CPU?, even top level switches will struggle if this means over any type of network layer.

[edmundhonda]

That's pretty impressive for integrated graphics.

"Sometime next year we'll have something that's on par with the £80 Ryzen part that's been out since February"

The weird part to me is presenting this as some step forward when they've shipped mobile APUs quicker than 1TFLOP already; the i7-6970HQ (72 EUs) is at ~1.2TFLOPS and there's Xeons clocked a little higher. I guess they've decided desktop users get the option now?

[DanceswithUnix]

People complain when Intel put a thermal compound rather than solder on top of a CPU die, and now Intel are putting other (heat generating) silicon on top? This will end well

[Valsined]

10 petaflops of compute
Is that double or single precision or is it 4 bit. Raja Koduri is once again overpromising.

[Corky34]

People complain when Intel put a thermal compound rather than solder on top of a CPU die, and now Intel are putting other (heat generating) silicon on top? This will end well

As long as they don't penny pinch buy putting poor quality other (heat generating) silicon on top I'm sure it will be fine.

[DanceswithUnix]

"10 petabytes of data within 10 milliseconds to every person" what this really means? data transfer speed inside the CPU?, even top level switches will struggle if this means over any type of network layer.

I think part of it is a sales goal, so sell more chips and your total bandwidth sold goes up. That makes it pretty meaningless as a goal, I think I would be more impressed if the picture was captioned "Jim Keller explains that he is a little teapot and here is his handle" as that is a cracking handle he has going on there, and I'm sure when he got the "here's my spout" he would have utterly nailed it.

Did Hexus choose two pictures with two ex AMD peeps in them, or was that just who Intel put forward?

[Tarinder]

I think part of it is a sales goal, so sell more chips and your total bandwidth sold goes up. That makes it pretty meaningless as a goal, I think I would be more impressed if the picture was captioned "Jim Keller explains that he is a little teapot and here is his handle" as that is a cracking handle he has going on there, and I'm sure when he got the "here's my spout" he would have utterly nailed it.

Did Hexus choose two pictures with two ex AMD peeps in them, or was that just who Intel put forward?

Raja and Jim - who are also both ex-Apple - were two of the leading spokespeople during the event.

[Platinum]

So they're moving to Chiplets like AMD. They've even not tried calling their 22nm I/O die an I/O die like AMD has. It sounds like Intel had a shelved chiplet design, saw what AMD has done and has unshelved it because if AMD hadn't done this with the Zen 2 lineup, they might have continued with the standard monolithic approach.

This is taking what AMD have done and going one step further by stacking the chips and cleverly integrating the chipset into the interposer die rather than having it just dumb silicon like AMD did with Vega.

[Platinum]

"Sometime next year we'll have something that's on par with the £80 Ryzen part that's been out since February"

This is the GT2 part though, there will likley be a GT3 "Iris" part which if historical parts are anything to go by will have 128 eus, that should beat even Vega 11, how it will stack up against Ryzen 3xxx APU's with Navi though is anyones guess.

Either way, this will be a big boost to most Laptop users who will buy a machine with an Intel chip and use the integrated graphics.

[Tabbykatze]

This is taking what AMD have done and going one step further by stacking the chips and cleverly integrating the chipset into the interposer die rather than having it just dumb silicon like AMD did with Vega.

I wouldn't call it clever, I would call it overly expensive and runs a extra risk of inflated failure rates. Some of the reasons why vega was so expensive was HBM chips and the interposer. The actual vega chip itself was relatively cheap. AMD did also suffer issues with the interposer which Intel may be able to overcome.

What I do estimate is these chips will not be cheap.

[Platinum]

I wouldn't call it clever, I would call it overly expensive and runs a extra risk of inflated failure rates. Some of the reasons why vega was so expensive was HBM chips and the interposer. The actual vega chip itself was relatively cheap. AMD did also suffer issues with the interposer which Intel may be able to overcome.

What I do estimate is these chips will not be cheap.

Lets wait and see, from what I can tell we wont be seeing them in out PC's any time soon, they are aimed at the low power fanless designs.
If I had to guess I would say the one they demo'd was for either Microsoft for a low power Surface or Apple for the 12" Macbook.

[Tabbykatze]

Lets wait and see, from what I can tell we wont be seeing them in out PC's any time soon, they are aimed at the low power fanless designs.
If I had to guess I would say the one they demo'd was for either Microsoft for a low power Surface or Apple for the 12" Macbook.

Yeah, Hexus' new article does indicate that these are not mainstream consumer chip and are instead looking at competing with the low powered ARM areas whom have been using a BIG.little design for mobile devices for nearly 10 years (2011) and it is very effective.

If Microsoft do continue mucking about on ARM then this could cause another gap in Intels revenue flow because then Microsoft Windows owners can start getting cheaper low power ultrabooks (which is big market apparently, look at chromebooks). So it is reasonable that Intel is trying to claw their way back out of the sinking sand they currently are finding themself in.

But making Foveros apply to big chips sounds very expensive.

[DanceswithUnix]

AMD did also suffer issues with the interposer which Intel may be able to overcome.

Intel use EMIB packaging, not an interposer. Multi chip modules have been around for decades, usually to reduce costs and almost never require an interposer. Vega only needs one because of the multiple HBM stacks on package.

The fundamental limit here is that stacking stuff on top of a 90W part won't work as it adds heat rather than takes it away. So this is a technology for 15W laptop parts, which isn't going to get me excited. But then to Intel ultra thin laptops are all that matters, so I can't say I am surprised.

[Corky34]

Multi chip modules have been around for decades, usually to reduce costs and almost never require an silicon interposer.

FTFY.

The fundamental limit here is that stacking stuff on top of a 90W part won't work as it adds heat rather than takes it away. So this is a technology for 15W laptop parts, which isn't going to get me excited. But then to Intel ultra thin laptops are all that matters, so I can't say I am surprised.

GN sat down with David Kanter to talk about the 3D stacking and the heat issues surrounding it in this video, Intel seem fairly confident a lot of the issues can be worked around with good design.