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Thread: JEDEC releases final specification for DDR5 SDRAM

  1. #17
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    Re: JEDEC releases final specification for DDR5 SDRAM

    at the start, for first year it will be behind price wall anyway

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    Re: JEDEC releases final specification for DDR5 SDRAM

    honesty, everyone is much to forgiving when it comes to JEDEC. DDR5 was suppose to be in the market 3 years ago. And since most people give them a pass ALL the time, for decades, those who do not put pressure on them to SPEED things up, you are slowing the industry down from progress. It's that way in every aspect of this industry, and should not be that way in this century. There is no valid reason why so many delays should occur, hire new engineers. Pick up the pace with releases already, and keep pace with market demand.

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    Re: JEDEC releases final specification for DDR5 SDRAM

    Quote Originally Posted by six_tymes View Post
    honesty, everyone is much to forgiving when it comes to JEDEC. DDR5 was suppose to be in the market 3 years ago. And since most people give them a pass ALL the time, for decades, those who do not put pressure on them to SPEED things up, you are slowing the industry down from progress. It's that way in every aspect of this industry, and should not be that way in this century. There is no valid reason why so many delays should occur, hire new engineers. Pick up the pace with releases already, and keep pace with market demand.
    Yeah that's the last time I buy something from JEDEC. Oh, wait.

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    Re: JEDEC releases final specification for DDR5 SDRAM

    Quote Originally Posted by kompukare View Post
    There fixed that for you!

    Certainly for affordable DDR5 - and for that matter DDR5 which actually offers a tangible improvement on current top-of-the-range DDR4.

    PCIe 5.0 and USB 4.0 might be possible but PCIe 4.0 is currently mostly under-utilised (headline burst rates for NVMe drives are about as useful headline burst rates for SATA3, SATA2, SATA1, PATA133, and so on - that is not very).

    5nm should happen in 2021, but not for everything as the prices of designs, masks etc. are even worse than 7nm. From the performance of the coming Zen2 APUs it is clear that a monolithic design has many advantages, and while AMD's increasing volume means it would make sense for them to return to monolithic for mainstream, the increased costs at 5nm make that very unlikely.
    Monolithic for mainstream would take away a good use for lower binned server chiplets, and it'd mean either a two die launch if they stick to the CPU-APU-CPU cycle or having the HEDT & server chips a whole CPU generation ahead of desktop

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    Re: JEDEC releases final specification for DDR5 SDRAM

    so elsewhere this came up again as mentioned by Hexus too: "DDR5 will operate at 1.1V, down from 1.2V for DDR4. DDR5 will also employ an on-DIMM voltage regulator. This means that motherboards supporting DDR5 won’t need to regulate DIMM voltage. This likely has implications for the cost/complexity of the DIMMs."

    Not only cost implications but if not done well could this affect overclocking, or even just the ability to set and lock your system to a given performance under or over? Will the user get any control over the settings?
    If you can't set and fix a voltage to prevent it getting frazzled when something automatically wants to take it too high - eg mobo auto overclocking which I've never found to work in a way I'd consider safe,
    Ditto for stupid XMP profiles that demand a voltage by default that I've often found to be unnecessary and that standard voltages usually work just fine (set manually and locked).
    Will this change limit ability to undervolt for cooler running?
    Then there are the extreme OC crew who will want to sail these things far outside of their intended waters. Is this impeded by this? If the voltage is set on-RAM then presumably RAM manufacturers will err on the side of caution out of warranty fears and put in place hard caps users simply can't bypass?

    There needs to be a manual control/override for this IMO. Cost issues aside I can see some pitfalls with this. I don't like the thought of trying to get a stable OC where the RAM is continually adjusting its own voltage.

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