Intel takes wraps off its 10nm SuperFin technology

[edmundhonda]

Charlie has quite a positive overview on Intel's process tweaks https://semiaccurate.com/2020/08/13/...and-packaging/

"Actually, they planned for 10nm to be dogrubbishrubbishrubbishrubbish for 2 years, here's a marketing slide from 2017 that proves it" is quite a stretch. As is:

Why is not a topic for today but just be aware that if Intel wanted to, 10nm products could have been significantly lower power than they ended up on the shelf as, plus this would have increased yields significantly.

One from the past wrt 14nm++ https://en.wikichip.org/w/images/0/0...14nm%2B%2B.png

[QuorTek]

well when the 7nm and lower goes into mature processes.. then you can see the big thing going on... for how long has Intel been on 14nm and 10nm? 10 years or more or something?

[watercooled]

Hmm, have Intel made a spelling mistake on their slide here: https://images.anandtech.com/doci/15...20%2810%29.jpg

In the context I'd assume they mean scalar, not scaler?

[Corky34]

Is SuperFin The Deep's sidekick?

Yes that's a shameless The Boys pun.

[DanceswithUnix]

"Actually, they planned for 10nm to be dogrubbishrubbishrubbishrubbish for 2 years, here's a marketing slide from 2017 that proves it" is quite a stretch. As is:

Well yeah, that slide only shows 10nm+ being as fast as 14nm++, whereas in reality I've lost count of how many plusses I am supposed to put after the 14 now.

But still, for a Charlie article it seemed quite pro Intel to me.

[DevDrake]

so when they done with 10nm AMD will be advancing to 5 and 3nm?

remember that intel/tsmc/globo nodes are different things, and are not comparable 1:1

[albert89]

I fear Intel might have rearranged things so that
they can shrink the dam thing down at the cost of
latency. In effect, requiring fast RAM to compensate.

[kalniel]

I fear Intel might have rearranged things so that
they can shrink the dam thing down at the cost of
latency. In effect, requiring fast RAM to compensate.

I don't understand your logic. Moving to smaller nodes has no direct bearing on anything like 'latency' - and in fact I'm not even sure what you mean when you say latency.

The best I can come up with is you're suggesting Intel's new designs will stop being able to look up caches and therefore need to go into RAM more often, which is about the only scenario I can think where fast RAM would compensate. But there's no reason why Intel would suddenly scrap or lower caches on new designs, and certainly no reason that would happen as a result of moving to a smaller process node - quite the opposite - cache is one of the main beneficiaries of node shrinks so you often get more rather than less.