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Thread: Intel pondering purchase of RISC-V chip designer SiFive

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    Re: Intel pondering purchase of RISC-V chip designer SiFive

    Quote Originally Posted by supremelaw View Post
    I'm really out of my league on this subject. Nevertheless, my "Way Back Machine" tells me that HP attempted a major push with RISC (reduced instruction set computing) several years back.
    Everyone switched to RISC not just HP, though their PA-RISC was pretty decent in its day. We are now surrounded by billions of RISC chips, and a few PCs running an evolution of x86 that tries to be as RISC like as possible. But even in a PC: each SSD has a handful of RISC cores, the GPU has a RISC command processor. Heck, even my mouse has a 32 bit ARM core in it.

    HP more recently tried (with Intel) to switch to the Itanium family which was a VLIW design. That flopped, making HP probably the worst poster child for RISC in the end.

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    Re: Intel pondering purchase of RISC-V chip designer SiFive

    https://forums.tomshardware.com/threads/risc-v-evolving-to-address-supercomputers-and-ai.3707916/

    Someone will need to translate the Comment appended to the article above,
    beginning: "Intel making a bid to buy SiFive might be good for the two of them,
    but I can't help but wonder how it will be good for RISC-V?"

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    Re: Intel pondering purchase of RISC-V chip designer SiFive

    Quote Originally Posted by DanceswithUnix View Post
    Everyone switched to RISC not just HP, though their PA-RISC was pretty decent in its day. We are now surrounded by billions of RISC chips, and a few PCs running an evolution of x86 that tries to be as RISC like as possible. But even in a PC: each SSD has a handful of RISC cores, the GPU has a RISC command processor. Heck, even my mouse has a 32 bit ARM core in it.

    HP more recently tried (with Intel) to switch to the Itanium family which was a VLIW design. That flopped, making HP probably the worst poster child for RISC in the end.
    IIRC the original AMD Athlon CPU's were a RISC core with x86 decoder(s)
    IMO all CPU's are now RISC - Intel's uOps are effectively a RISC instruction set of their own.......
    "In a perfect world... spammers would get caught, go to jail, and share a cell with many men who have enlarged their penises, taken Viagra and are looking for a new relationship."

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