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Thread: AMD provides more 3D stacking info at Hot Chips 33

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    AMD provides more 3D stacking info at Hot Chips 33

    And a leaked document confirms AMD AM5 will support DDR5 and PCIe 4.0 (not 5.0).
    Read more.

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    Re: AMD provides more 3D stacking info at Hot Chips 33

    4x4.0 lanes for the USB 4 controller means you can have either one full speed 40gbps USB4 socket or two USB4 sockets operating at a shared speed maxing out at a theoretical top end of 64gbps, that's not bad. Obviously if it were PCIe 5.0 it would be 40gbps for both but I don't think AMD is losing out not going to 5.0 on the desktop (yet) and that's because it's not the same like the jump between 3.0 and 4.0. On 3.0 we were starting to see strain on all resources around the system as storage, GPU and other add-ins were all starting to consume quite a lot of bandwidth. With 4.0 we're not seeing that yet unless you are stocking your system up chock full of 4.0 SSDs and even then the difference between a 3.0 and 4.0 SSD can be "measured" in a human term but we're not really stressing 4.0 speeds yet so 5.0 speeds aren't observably going to much of a difference yet.

    Also, 4.0 SSD controllers are still going through a substantial amount of iterative improvements and the cooling needed for higher end 4.0 SSDs will likely make it even harder for 5.0 SSDs to operate in the same way, we might see "mid range" 5.0 SSDs needing stronger cooling than their 4.0 "mid range" previous gen counterparts.

    I suspect AMD didn't go for 4.0 this time because of the above and also because the signal doublers and resignalers (can't remember the term, the hardware you use to keep signal strength and quality over a distance) were a PITA for 4.0, 5.0 is only going to make it harder again. So we could see a flip back from AMD mobos being more expensive initially on release than the intel counterparts to being cheaper because of the opt for 4.0 compatibility.

    But are we going to see again when AMD moves to PCIe 5.0 where the 4.0 AM5 boards could "theoretically" run at 5.0 speeds but AMD decides to lock it out. I actually agreed with AMDs lockout because people will enable the functionality, potentially have a poor experience with the board and then blame AMD/board manufacturer for an experience that was never meant to happen in the first place (the leaked BIOS was just testing and verification IIRC). I wanted them to allow it but have the BIOS display a full screen 10 second warning saying "your board is not specced for 4.0, yes it may be able to run it but if it doesn't work very well or breaks, it's on you for trying it out"

    We'll see if Intels utilisation of 5.0 does them any favours but last I heard in July, Intels board partners were going through the ringer with 5.0.

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    Re: AMD provides more 3D stacking info at Hot Chips 33

    PCIe 4.0 versus 5.0 is all about bragging rights at this moment in the tech cycle. PCIe 4.0 has enough bandwidth to contain the current, and near future peripherals.
    3 or 4 years down the line....that may change.

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    Re: AMD provides more 3D stacking info at Hot Chips 33

    In the general consumer market that is.

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    Re: AMD provides more 3D stacking info at Hot Chips 33

    Quote Originally Posted by ohmaheid View Post
    PCIe 4.0 versus 5.0 is all about bragging rights at this moment in the tech cycle. PCIe 4.0 has enough bandwidth to contain the current, and near future peripherals.
    3 or 4 years down the line....that may change.
    Agreed!

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    Re: AMD provides more 3D stacking info at Hot Chips 33

    Quote Originally Posted by Tabbykatze View Post
    ....and that's because it's not the same like the jump between 3.0 and 4.0. On 3.0 we were starting to see strain on all resources around the system as storage...
    I thought, incorrectly it seems as i can't find any info, that 5.0 was a more drastic change than 3 - 4. I could've sworn that i read that 5.0 needed physical changes like having a repeater/booster/retimers and much stricter isolation of the physical traces on the board.

    The chances are I'm misremembering but on the off chance I'm not going to 5.0 seems like it maybe an unneeded extra cost.

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    Re: AMD provides more 3D stacking info at Hot Chips 33

    Quote Originally Posted by Corky34 View Post
    I thought, incorrectly it seems as i can't find any info, that 5.0 was a more drastic change than 3 - 4. I could've sworn that i read that 5.0 needed physical changes like having a repeater/booster/retimers and much stricter isolation of the physical traces on the board.

    The chances are I'm misremembering but on the off chance I'm not going to 5.0 seems like it maybe an unneeded extra cost.
    Yeah, that's what I'm getting at, the supporting electronics for 5.0 are by and far much bigger than the electrical needs of 4.0 as we're getting closer and closer to the diminishing returns of high frequencies being disrupted even over short distances.

    Hell, on another note we're only starting to see properly certified PCIe 4.0 riser cables and even then they're really expensive and only from a few manufacturers I'd trust.
    Last edited by Tabbykatze; 23-08-2021 at 12:14 PM.

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    Re: AMD provides more 3D stacking info at Hot Chips 33

    At the current supply chain meltdown we need Pcie 5.0 on the desktop and laptop for no reason. can two 3090s saturate Pcie 4.0?

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    Re: AMD provides more 3D stacking info at Hot Chips 33

    Quote Originally Posted by lumireleon View Post
    At the current supply chain meltdown we need Pcie 5.0 on the desktop and laptop for no reason. can two 3090s saturate Pcie 4.0?
    Meh, not really.

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    Re: AMD provides more 3D stacking info at Hot Chips 33

    The only advantage going with PCIe gen5 might add is not needing to give each device as many lanes and supporting more SSDs and so on.

    Intel gains bragging rights, but the gen5 is really for the workstation and data center markets than consumer.
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    Re: AMD provides more 3D stacking info at Hot Chips 33

    Quote Originally Posted by kellyharding View Post
    The only advantage going with PCIe gen5 might add is not needing to give each device as many lanes and supporting more SSDs and so on.

    Intel gains bragging rights, but the gen5 is really for the workstation and data center markets than consumer.
    It doesn't really work that way unless you homogenise all the PCIe lanes into one big PLX (or something akin) multiplexer that can do sensing and down grade the PCIe version of a connected peripheral if it detects its a lower PCIe need so therefore the bandwidth can be saved and shared across other devices. That is very complex and very expensive and likely will not be seen anything outside of high end workstation or "phat" servers. A PCIe lane is a PCIe lane, it can run at 2, 3, 4 or gen 5 speeds, it's not a bandwidth/lane pool.

    But with AMD throwing 128 lanes on the table from the off, it makes it much simpler.

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