AMD spills more details on HBM memory

[HEXUS]

As found on the upcoming Radeon R9 390X 'Fiji' GPU.

Read more.

[Guppy]

I'm holding off getting a new graphics card as I'm eagerly anticipating AMDs new high end cards. Here's hoping they're competitive.

[sykobee]

In addition there are rumours that AMD is trialling dual-link HBM - two stacks of DRAM (2GB) upon a single base logic die that performs the routing logic between the DRAM stacks. This would allow them to get to 8GB with Fiji, but maybe it will be a month or two later than the 4GB versions.

[Ulti]

Can't this HBM memory technology be applied to everything? I.e. RAM too? Or does GDDR and HBM differ too much from conventional desktop RAM? But then again you could argue that the RAM is very rarely a bottleneck for desktop systems and even increasing the speeds will not give much performance increase compared with the CPU or GPU for most tasks.

[Tpyo]

Possible typo - use 2Gb slices resulting in 256MB - is this meant to be 256 mb slices resulting in 2GB?

[shaithis]

Possible typo - use 2Gb slices resulting in 256MB - is this meant to be 256 mb slices resulting in 2GB?

Note the case of the letter B

8b = 1B (or 8 bits = 1 Byte)
2Gb = 0.25 GB = 256MB

[scaryjim]

Can't this HBM memory technology be applied to everything? ...

Yes, as alluded to by this line near the end of the article:

... AMD has apparently solved the HBM design and implementation problem that will eventually fall to all who need to use memory for processors. The implications are far-reaching, from Nvidia to Intel to ARM, but, right now, HBM may not quite be that appetising free lunch it first appears.

A memory interface is a memory interface. Where AMD are right now they could make an entire system on a single interposer, with APU, southbridge, HBM - they could probably even work out a way to stick 32GB of flash memory on there too. Whether such a device would be economically viable is another matter entirely. And of course some people will always want their system RAM upgradeable, which an HBM-based system wouldn't be. But assuming AMD actually get this to market in decent volume, the proof will be there for it be expanded to other products. An APU with 1GB of HBM on-interposer as a graphics cache would be pretty remarkable, for instance....

[shaithis]

An APU with 1GB of HBM on-interposer as a graphics cache would be pretty remarkable, for instance....

I'm still not sure. We have seen what happens to an APU when the RAM bandwidth limitation is pretty much removed (PS4) and the difference isn't night and day. PS4 uses GDDR5 and has more streams, yet is only slightly faster than the XB1 with DDR3 RAM.

My hope for this tech is probably pie in the sky: Move RAM from the GPU to the system and then enable HSA on non-APU systems. I.e. a universal system-wide memory architecture.

[kalniel]

My hope for this tech is probably pie in the sky: Move RAM from the GPU to the system and then enable HSA on non-APU systems. I.e. a universal system-wide memory architecture.

Like consoles do?

[shaithis]

Like consoles do?

Indeed but on non-APU systems. Would make the choice of components a lot more flexible and allow upgrades you just cannot do at the moment, as well as potentially making upgrades cheaper and more granular then they currently are.

[Plasmastorm]

Remember when Nvidia had the issue with GPU solder joints on laptop gpu's failing over time. Something in the back of my head is telling me HBM may have similar problems down the line.
Hope not but I'm wary tbh.

[Rebo00]

Possible typo - use 2Gb slices resulting in 256MB - is this meant to be 256 mb slices resulting in 2GB?

It's not a typo, it's correct. As Shaithis has broke down for you. 2Gb per chip, 4 chips in a stack result in 1GB stacks.
Max of 4 stacks supported gives you the max of 4GB

Andy

[Jace007]

Sykobbe your right I read that a few months ago too, its taken a long 7 years to develop these 1st gen HBM and they had many issues with them. Lets see if the higher bandwidth these provide makes a difference at being capped at 4GB. I got a feeling it wont make a marginal difference to initial performance but rather to Cost/ per watt. Putting x2 of these on Crossfire should be real intresting

[kalniel]

Indeed but on non-APU systems. Would make the choice of components a lot more flexible and allow upgrades you just cannot do at the moment, as well as potentially making upgrades cheaper and more granular then they currently are.

While I think it'd be more flexible for system creators, I think upgrades would be less granular - you'd have to swap out your system on an interposer rather than just the RAM or CPU.

[scaryjim]

Big problem with moving RAM away from the GPU is that you have round trips across whatever interface the GPU is connected by to factor in. Even if PCIe 4 was available now and GPU manufacturers started using the full permissible 32 lanes (which would require Intel and AMD to make those available on their chipsets/motherboards/CPUs) you'd be topping out at 63GB/s bandwidth, which is less than available to the xbox one. And AFAIK PCIe is fairly high latency, so you'd need very good prefetch routines to avoid stalling.

As to HSA for non-APU systems, AFAIK it already exists: HSA is theoretically hardware-vendor agnostic, as long as that hardware meets the system architecture requirements for HSA. It doesn't actually matter how the memory is attached to your devices: the whole point of HSA is to view the aggregate resources in your entire system as one space: one set of memory, one set of processors, then allocate the tasks to whichever processors are best suited to handle them. it doesn't require the memory to not be attached to certain devices, as long as those devices allow the HSA software to access the memory correctly.

[DanceswithUnix]

My hope for this tech is probably pie in the sky: Move RAM from the GPU to the system and then enable HSA on non-APU systems. I.e. a universal system-wide memory architecture.

Graphics ram is high bandwidth, CPU ram is low latency. If you want the best performance, then you want the best tool for the job. Making use of this technology on a CPU would want a different memory, Low Latency Memory LLM perhaps.