Read more.Available in Q3.
Read more.Available in Q3.
If Threadripper socket is only quad channel memory, I wonder if you only get 1 memory channel per die to balance things or if they leave 2 dies without any ram access so that lightly threaded work gets full memory width.
Is the socket quad-channel only, though? If the DIMM slots are each wired directly to the socket then the CPU could potentially address all 8 as separate channels. Unless I'm misunderstanding how multiple DIMMs per channel are typically wired, that is.
EDIT! Nevermind, just checked the specs. Definitely quad-channel only.
Last edited by afiretruck; 06-06-2018 at 07:47 AM.
Technically speaking what we think of as the cores (four of them per CCX) don't communicate directly with the ram (or any external I/O), any off CCX data gets sent to the CCM whose job it is to place that data onto the SDF, it then gets taken off the SDF by a UMC and it's the UMC that communicates with the RAM, i guess you could get a bottleneck what with eight CCM's trying to feed four UMC's, I've not done the maths.
Last edited by Corky34; 06-06-2018 at 08:43 AM.
The problem is things slow down when you go off chip, so if a core wants memory that is on another die then that request has to go off die to the memory controller on the other die. Going across a carrier in a package is way better than going socket to socket across a PCB, but there will still be a cost despite the best efforts of the ram prefetchers.
I'm guessing AMD already did the maths, which is why Epyc has 8 ram channels for 4 dies, normal Ryzen has 2 channels for 1 die.
Now you've got me confused, if a core wants to access data located within the local memory of another core on another CCX it would go via the CCM's, the memory controllers are not part of the dies, as in the four cores that make up a CCX can only talk directly to either one of the other three core (and their associated local memory (L1, 2, 3) or they can talk to that CCX's CCM.
Because ZEN was designed as a SoC the actual cores are pretty dumb as IF deals with all the communication that happens outside each group of four cores, including the memory controllers (UMC's) and any I/O request, if a core want's memory that's on another die it depends where that other die is, if it's within the same CCX it does it directly, if it's anywhere else a request is made to that CCX's CCM and the CCM places the request on the SDF for either another CCM or a UMC to take it off.
Basically the cores themselves don't have direct access to the DDR memory controllers (the UMC's) or even another CCX's CCM.
If the price is right I might actually replace my "work" pc which is still on a Xeon X5645 + 12 gigs
Old puter - still good enuff till I save some pennies!
Interesting times, cant wait to see the 28 core i9 go head to head with the 32core TR2.
at 5GHz though the 28 core will probably be slightly faster overall, but probably also 3x the price lol.
KN1GHT (07-06-2018)
KN1GHT (07-06-2018)
Old puter - still good enuff till I save some pennies!
Watch your terminology here. The memory controllers are not part of the CCX, but they are part of the die. Communication from a CCX on a die to the memory controller on the same die happens across a tiny piece of silicon. For that CCX to communicate with a memory controller on a different die on the same package crosses a much greater distance through traces and additional connections. That adds latency, and when you're talking about timespans of less than 100ns, that additional latency is going to be signficant - each nanosecond is a > 1% delay.
Corky34 (06-06-2018),DanceswithUnix (06-06-2018)
Quite, I think there is some confusion here.
This is a Ryzen die, a lump of silicon cut from a wafer and the basic building block here:
Threadripper used to have two of these in a package, Epyc had four in a package and in both cases fully connected. Now it seems that Threadripper will be an Epyc with some memory channels omitted and in some use cases that will matter.
scaryjim (06-06-2018)
https://www.anandtech.com/show/12906...w-x399-refresh
Apparently 2 of the dies will have their memory channels disabled and will expect to utilise the infinity fabric for memory access. So the "first" 16 cores will retain full bandwidth and the further 16 will have increased latency.
I tend to agree with the article in that, if the latency is going to be an issue for you, buy Epyc. As long as the scheduler in windows knows how to allocate correctly, I cant imagine there will be too many workloads affected by the additional latency.
Looking at that and the prices mooted I'd probably stick with a 16c32t chip with Zen+ architecture. I'd guess and say that it would give me a huge boost without breaking the piggy bank. Will probably boost to 4ghz as well rather than 3.4 ghz for some lower thread action
Old puter - still good enuff till I save some pennies!
There are currently 1 users browsing this thread. (0 members and 1 guests)