AMD video focuses on its 3D stacking technology

[HEXUS]

Provides some further background info on the 3D V-Cache TSV construction process.

Read more.

[Xlucine]

So did AMD design a new CCD design with TSVs squeezed into it, or have they been hiding in shipping zen 3 dies all this time?

[CAT-THE-FIFTH]

So did AMD design a new CCD design with TSVs squeezed into it, or have they been hiding in shipping zen 3 dies all this time?

IIRC,I recently saw some pictures which showed they have always been there.

[Tabbykatze]

IIRC,I recently saw some pictures which showed they have always been there.

https://www.reddit.com/r/AMD_Stock/c...ocated_in_the/

That's actually really impressive that they were that confident in the tech they modified their CPUs with preliminary support and shipped an entire processor family on the offchance they'd have it ready before its life cycle ends and can double up the R&D costs without having to make custom silicon/tape outs.

Pullout of the actual Twitter thread:
https://twitter.com/HansDeVriesNL/st...27736199081989

And the video:

[Xlucine]

That's actually really impressive that they were that confident in the tech they modified their CPUs with preliminary support and shipped an entire processor family on the offchance they'd have it ready before its life cycle ends and can double up the R&D costs without having to make custom silicon/tape outs.

A less charitable way of looking at it would be that it's taken them 7 months longer than they initially expected to get this to work...

If ryzen 5000 launched with the cache ice & rocket lake would have fallen a lot flatter

[Tabbykatze]

A less charitable way of looking at it would be that it's taken them 7 months longer than they initially expected to get this to work...

If ryzen 5000 launched with the cache ice & rocket lake would have fallen a lot flatter

That is very true.

If that were the case, I wonder where the hold up was, was it with TSMC and their TSV technology or AMD for the integration. As there appears, and said, that there are no design changes for the CCD I would assume it would be either a logistical problem or a problem with cache die integration.